XJTAG DFT Assistant is composed of two key elements: XJTAG Chain Checker and XJTAG Access Viewer. XJTAG Chain Checker identifies common errors in a JTAG scan chain, such as incorrectly connected and terminated test access ports (TAPs), and reports them to the developer. Otherwise, a single connection error would inhibit the entire scan chain from working. XJTAG Access Viewer overlays the extent of boundary scan access onto the schematic diagram, allowing users to instantly see which components are accessible using boundary scan, and where test coverage can be further extended. Engineers can highlight the nets individually to show read, write, power/ground and the nets without any JTAG access on the schematic.
"We need to determine early in the design phase how to maximize test coverage using the minimum number of test points, so it is vital to know what JTAG access is available at the schematic stage," said Urs Allemann, director of design services at ed electronic design ag. "The XJTAG DFT Assistant for OrCAD Capture makes it easy for us to see the test coverage as the design evolves. This allows us to optimize our testing before the PCB is produced."
While the first prototype is being manufactured, XJTAG DFT Assistant allows engineers to export a preliminary XJTAG project from OrCAD Capture to the XJTAG development software, where additional tests can be developed. Hardware can then be tested as soon as it is available.
XJTAG DFT Assistant software is now included with OrCAD Capture 17.2-2016 QIR 2 at no additional cost; users of version 17.2 or higher can download the software today from www.xjtag.com/orcad.
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SOURCE Cadence Design Systems, Inc.