New MultiBench(TM) Multicore Benchmarks Now Available From EEMBC(R)

    EL DORADO HILLS, Calif., April 1, 2008 /PRNewswire/ -- The Embedded
 Microprocessor Benchmark Consortium today announced the availability of a
 new suite of embedded benchmarks that allows processor and system designers
 to analyze, test, and improve multicore architectures and platforms. The
 new EEMBC(R) MultiBench(TM) tool uses standardized workloads and a test
 harness that provides compatibility with a wide variety of multicore
 embedded processors and operating systems.
 
     Leveraging EEMBC's proven library of application-focused benchmarks in
 hundreds of workload combinations, MultiBench workloads can be
 parameterized individually to vary the amount of concurrency being
 implemented by the algorithm. By applying incrementally challenging
 workloads, MultiBench allows the testing of scalability and bottlenecks
 within the system. Beyond helping designers to optimize programs for
 specific processors and systems, MultiBench allows users to assess the
 impact of memory bottlenecks, OS scheduling support, efficiency of
 synchronization, and other related functions in systems using multicore
 processors.
 
     "Putting multiple execution cores into a single processor does not by
 itself guarantee greater multiples of processing power, and there is no
 prima facie reason to expect that a multicore processor will deliver a
 dramatic increase in a system's capabilities, computing resources, or
 throughput," said EEMBC President Markus Levy. "This is why MultiBench is
 so important. It's designed to show when parallelization and scaling
 contribute to performance -- and when and why they don't."
 
     MultiBench Version 1.0 targets the evaluation of scalable symmetrical
 multicore processor (SMP) architectures with shared memory. It uses a
 thread- based API to establish a common programming model. The suite's
 individual benchmarks target three forms of concurrency: data
 decomposition, multiple data stream processing, and processing of multiple
 workloads. Data decomposition allows multiple threads to cooperate on
 achieving a unified goal and demonstrates a processor's support for fine
 grain parallelism. Processing of multiple data streams uses common code
 running over multiple threads and demonstrates how well a solution can
 scale over scalable data inputs. Finally, multiple workload processing
 shows the scalability of a solution for general- purpose processing and
 demonstrates concurrency over both code and data.
 
     To implement this strategy on the benchmark level, EEMBC has developed
 a unique test harness that communicates with the benchmark through an
 abstraction layer and provides a flexible interface to allow a wide variety
 of thread-enabled workloads to be tested. The test harness also provides a
 convenient mechanism by which to easily create new workloads composed of
 different kernels or using different datasets. The EEMBC Technology Center
 offers analysis of MultiBench results as one of its testing services, which
 are described in a separate press release issued today.
 
     To construct the hundreds of workloads that are available in MultiBench
 as individual tests, EEMBC has drawn on the full range of its
 industry-standard benchmarks addressing the real-world demands of
 automotive, digital entertainment, digital imaging, networking, telecom,
 and office automation systems. In addition, EEMBC has created several new
 parameterizable benchmarks specifically focused on multicore for
 demonstrating data decomposition. The wide variety of workloads supports
 judicious monitoring of parameters that highlight the strengths and
 weaknesses of any multicore processor and system.
 
     EEMBC's MultiBench multicore-enabled benchmarks are available for
 licensing now. Further information is available at http://www.eembc.org.
 
     About EEMBC
 
     EEMBC, the Embedded Microprocessor Benchmark Consortium, develops and
 certifies real-world benchmarks and benchmark scores to help designers
 select the right embedded processors for their systems. Every processor
 submitted for EEMBC benchmarking is tested for parameters representing
 different workloads and capabilities in communications, networking,
 consumer, office automation, automotive/industrial, embedded Java, and
 network storage-related applications. With members including leading
 semiconductor, intellectual property, and compiler companies, EEMBC
 establishes benchmark standards and provides certified benchmarking results
 through the EEMBC Technology Center.
 
     EEMBC's members include Adaptec, Altera, AMD, Analog Devices, ARC
 International, ARM, Artifex Software, Atmel, Broadcom, Code Sourcery,
 esmertec, Freescale Semiconductor, Fujitsu Microelectronics, Green Hills
 Software, IAR Systems AB, IBM, Imagination Technologies, Improv Systems,
 Infineon Technologies, Intel, LSI Logic, Marvell Semiconductor, Matsushita
 Electric Industrial, Mentor Graphics, Microchip Technology, MIPS
 Technologies, National Instruments, NEC Electronics, NETCLEUS Systems,
 Nokia, NXP Semiconductors, Oki Electric Industry Co, PA SEMI, PMC-Sierra,
 Qualcomm, Realtek Semiconductor, Red Hat, Renesas Technology, Sony Computer
 Entertainment, ST Microelectronics, Sun Microsystems, Tensilica, Texas
 Instruments, Toshiba, VIA Technologies, and Wind River Systems.
 
     MultiBench is a trademark and EEMBC is a registered trademark of the
 Embedded Microprocessor Benchmark Consortium.
 
 
 

SOURCE EEMBC