Actel Broadens Flash-Based Offering; Announces Industry's Largest, Single-Chip FPGA Solutions

Products Reduce Risk and Improve Time to Market for ASIC Designers



Apr 10, 2001, 01:00 ET from Actel Corporation

    SUNNYVALE, Calif., April 10 /PRNewswire/ --
 Actel Corporation (Nasdaq:   ACTL) today announced it is sampling the A500K180
 and A500K270 flash-based ProASIC 500K field programmable gate array (FPGA)
 devices.  These devices, at 369,000 and 473,000 system gates, respectively,
 represent the highest density, non-volatile, single-chip, "live-at-power-up,"
 reprogrammable solutions on the market.  Actel's ProASIC FPGAs make it
 possible to create high-density systems using existing ASIC or FPGA design
 flows and tools, shortening time to production.  These new devices suit a
 range of system-critical applications such as optical networking, advanced
 avionics and industrial controls, in which instant-on operation is needed to
 ensure that power-on latency does not compromise system functionality.
     Implemented in a standard CMOS logic process, the A500K180 and
 -270 devices combine low power and flash-based non-volatility with an
 ASIC-like architecture that delivers predictable performance and great routing
 efficiency.  Specifically, the devices' unique routing hierarchy and structure
 enable up to 95 percent gate utilization as proven by Actel benchmarks and
 customer experience.  With this single-chip solution, engineers can use
 ProASIC devices to create designs that not only meet their system density
 requirements, but do so using the least amount of components and board real
 estate.
     "Our largest single-chip ProASIC devices are sampling at a time when
 system designers are looking for ways to improve the efficiency and
 functionality of their next-generation, high-end designs without the risks and
 high costs associated with ASICs," said Dennis Kish, vice president, marketing
 at Actel.  "For the first time, designers can have the best of all worlds
 -- high density, non-volatility and reprogrammability -- in a single device."
     The A500K270, the larger of the two devices at 473,000 system gates,
 offers nearly 27,000 flip flops and 65 kbits of RAM in 28 blocks of
 256 x 9 bits.  The 369,000-gate A500K180 offers more than 18,000 flip flops
 with 55 kbits of RAM in 24 blocks.  As with other members of the ProASIC 500K
 family, these new devices bring significant benefits to any designer of
 high-density logic.  For example, ProASIC is single-chip and
 "live-at-power-up," eliminating the need for a extra boot device such as a
 serial programmable read only memory (PROM) associated with SRAM FPGAs,
 thereby simplifying board design and cost.
     As a programmable device, the ProASIC family reduces time-to-market and
 minimizes design risk and investment, requiring no mask sets or silicon
 re-spins.  Unlike most other PLDs, ProASIC devices operate at very low power,
 using only one-half of the power consumed by static random access memory
 (SRAM) FPGAs and other PLDs based on look-up tables (LUTs) at the same supply
 voltage.
 
     Non-volatile, Single-Chip, Reprogrammable Solutions
     The ProASIC 500K family consists of four devices ranging in size from
 98,000 to 473,000 system gates and includes up to 65k bits of embedded
 two-port memory.  The ProASIC 500K family combines the advantages of ASICs
 with the benefits of PLDs through its non-volatile flash technology.
 Migration to an ASIC is made easy by ProASIC's ASIC-like design flow, which
 supports rapid verification against the original RTL test bench.
 
     Leverages Existing Design Methodology
     ProASIC is supported by industry-leading third-party synthesis, simulation
 and static timing tools from Exemplar Logic, Model Technology, Synopsys,
 Synplicity, Cadence and other leading EDA vendors.  The ProASIC software
 supports major operating systems, including Windows NT, Solaris, HP-UX and
 SunOS.
     The ProASIC place and route design tool was designed from the beginning to
 support both ASIC and FPGA design flows.  The tool set is based on a complex,
 multi-million gate-capable ASIC layout tool that includes timing-driven place
 and route (TDPR).  The software integrates a global router, static timing
 analyzer, 2 1/2 D-based RC extractor, asymptotic waveform extraction (AWE)
 delay calculator and an engineering change order (ECO) editor into an advanced
 design flow.  Additional capabilities include automated memory generation with
 the ProASIC MemoryMaster tool, power estimation and a layout viewer for
 identifying and optimizing critical paths.
 
     Pricing and Availability
     The A500K180 and A500K270 devices are currently available as engineering
 samples.  Commercial and industrial qualifications for the A500K180 and
 A500K270 devices are expected in Q3 2001.  Volume pricing for the A500K180
 starts at $56.30 and volume pricing for the A500K270 starts at $95.30.
 
     About Actel
     Actel is The Programmable ASIC Solutions Company.  Programmable ASICs
 (application specific integrated circuits) offer the benefits of both
 conventional ASICs (single chip and low power and price) and programmable
 logic devices (faster time to market plus reduced design and inventory risks).
 For customers requiring discrete programmable logic solutions, Actel's FPGAs
 (field programmable gate arrays) provide design security, are non-volatile and
 "live at power up."  For customers requiring embedded programmable solutions,
 Actel's intellectual property cores will enable the integration of
 reprogrammable logic functions in ASICs or ASSPs (application specific
 standard products) on standard processes.  Customers can further accelerate
 time to market by using Actel's Protocol Design Services Group.  Actel is
 traded on the Nasdaq National Market under the symbol ACTL and is located at
 955 East Arques Avenue, Sunnyvale, California, 94086-4533.
 Telephone:  888-99-ACTEL (992-2835).  Internet:  http://www.actel.com.
     NOTE:  ProASIC and the Actel name and logo are registered trademarks of
 Actel Corporation.  All other trademarks and service marks are the property of
 their respective owners.
 
 

SOURCE Actel Corporation
    SUNNYVALE, Calif., April 10 /PRNewswire/ --
 Actel Corporation (Nasdaq:   ACTL) today announced it is sampling the A500K180
 and A500K270 flash-based ProASIC 500K field programmable gate array (FPGA)
 devices.  These devices, at 369,000 and 473,000 system gates, respectively,
 represent the highest density, non-volatile, single-chip, "live-at-power-up,"
 reprogrammable solutions on the market.  Actel's ProASIC FPGAs make it
 possible to create high-density systems using existing ASIC or FPGA design
 flows and tools, shortening time to production.  These new devices suit a
 range of system-critical applications such as optical networking, advanced
 avionics and industrial controls, in which instant-on operation is needed to
 ensure that power-on latency does not compromise system functionality.
     Implemented in a standard CMOS logic process, the A500K180 and
 -270 devices combine low power and flash-based non-volatility with an
 ASIC-like architecture that delivers predictable performance and great routing
 efficiency.  Specifically, the devices' unique routing hierarchy and structure
 enable up to 95 percent gate utilization as proven by Actel benchmarks and
 customer experience.  With this single-chip solution, engineers can use
 ProASIC devices to create designs that not only meet their system density
 requirements, but do so using the least amount of components and board real
 estate.
     "Our largest single-chip ProASIC devices are sampling at a time when
 system designers are looking for ways to improve the efficiency and
 functionality of their next-generation, high-end designs without the risks and
 high costs associated with ASICs," said Dennis Kish, vice president, marketing
 at Actel.  "For the first time, designers can have the best of all worlds
 -- high density, non-volatility and reprogrammability -- in a single device."
     The A500K270, the larger of the two devices at 473,000 system gates,
 offers nearly 27,000 flip flops and 65 kbits of RAM in 28 blocks of
 256 x 9 bits.  The 369,000-gate A500K180 offers more than 18,000 flip flops
 with 55 kbits of RAM in 24 blocks.  As with other members of the ProASIC 500K
 family, these new devices bring significant benefits to any designer of
 high-density logic.  For example, ProASIC is single-chip and
 "live-at-power-up," eliminating the need for a extra boot device such as a
 serial programmable read only memory (PROM) associated with SRAM FPGAs,
 thereby simplifying board design and cost.
     As a programmable device, the ProASIC family reduces time-to-market and
 minimizes design risk and investment, requiring no mask sets or silicon
 re-spins.  Unlike most other PLDs, ProASIC devices operate at very low power,
 using only one-half of the power consumed by static random access memory
 (SRAM) FPGAs and other PLDs based on look-up tables (LUTs) at the same supply
 voltage.
 
     Non-volatile, Single-Chip, Reprogrammable Solutions
     The ProASIC 500K family consists of four devices ranging in size from
 98,000 to 473,000 system gates and includes up to 65k bits of embedded
 two-port memory.  The ProASIC 500K family combines the advantages of ASICs
 with the benefits of PLDs through its non-volatile flash technology.
 Migration to an ASIC is made easy by ProASIC's ASIC-like design flow, which
 supports rapid verification against the original RTL test bench.
 
     Leverages Existing Design Methodology
     ProASIC is supported by industry-leading third-party synthesis, simulation
 and static timing tools from Exemplar Logic, Model Technology, Synopsys,
 Synplicity, Cadence and other leading EDA vendors.  The ProASIC software
 supports major operating systems, including Windows NT, Solaris, HP-UX and
 SunOS.
     The ProASIC place and route design tool was designed from the beginning to
 support both ASIC and FPGA design flows.  The tool set is based on a complex,
 multi-million gate-capable ASIC layout tool that includes timing-driven place
 and route (TDPR).  The software integrates a global router, static timing
 analyzer, 2 1/2 D-based RC extractor, asymptotic waveform extraction (AWE)
 delay calculator and an engineering change order (ECO) editor into an advanced
 design flow.  Additional capabilities include automated memory generation with
 the ProASIC MemoryMaster tool, power estimation and a layout viewer for
 identifying and optimizing critical paths.
 
     Pricing and Availability
     The A500K180 and A500K270 devices are currently available as engineering
 samples.  Commercial and industrial qualifications for the A500K180 and
 A500K270 devices are expected in Q3 2001.  Volume pricing for the A500K180
 starts at $56.30 and volume pricing for the A500K270 starts at $95.30.
 
     About Actel
     Actel is The Programmable ASIC Solutions Company.  Programmable ASICs
 (application specific integrated circuits) offer the benefits of both
 conventional ASICs (single chip and low power and price) and programmable
 logic devices (faster time to market plus reduced design and inventory risks).
 For customers requiring discrete programmable logic solutions, Actel's FPGAs
 (field programmable gate arrays) provide design security, are non-volatile and
 "live at power up."  For customers requiring embedded programmable solutions,
 Actel's intellectual property cores will enable the integration of
 reprogrammable logic functions in ASICs or ASSPs (application specific
 standard products) on standard processes.  Customers can further accelerate
 time to market by using Actel's Protocol Design Services Group.  Actel is
 traded on the Nasdaq National Market under the symbol ACTL and is located at
 955 East Arques Avenue, Sunnyvale, California, 94086-4533.
 Telephone:  888-99-ACTEL (992-2835).  Internet:  http://www.actel.com.
     NOTE:  ProASIC and the Actel name and logo are registered trademarks of
 Actel Corporation.  All other trademarks and service marks are the property of
 their respective owners.
 
 SOURCE  Actel Corporation