Tera Systems Produces Major Upgrade to TeraForm RTL Design Planning Product Line

TeraForm 2001.1 Enables Logic Designers to Make High-Level RTL Optimizations

And Significantly Improve Chip Quality



Apr 30, 2001, 01:00 ET from Tera Systems, Inc.

    CAMPBELL, Calif., April 30 /PRNewswire/ -- Tera Systems, Inc., today
 announced a major upgrade to its TeraForm(R) RTL design planning solution,
 TeraForm 2001.1. Enhancements to the TeraForm analysis partitioning,
 floorplanning and timing-optimization capabilities solidify the product's
 status as the new front-end to today's gate-level, logic synthesis and layout
 solutions for high-performance system-on-chip (SOC) design.
     TeraForm is the first tool of its kind to give chip designers essential
 visibility and control over their chip's logical, physical and timing domains
 well ahead of gate-level synthesis and layout. Unlike other EDA approaches
 that require logic designers to learn how to do physical layout, TeraForm
 enables logic designers to focus on register-transfer level (RTL) design
 creation and optimization and then to hand-off a superior design to the
 physical implementation team. By producing a better starting point for
 existing gate-level synthesis and layout tools, TeraForm enables faster
 downstream design convergence with fewer iterations late in the design cycle.
     "Our customers -- both ASIC designers and vendors -- have seen the value
 of TeraForm across numerous SOC designs since we first introduced it in 1998,"
 said Tommy Eng, president of Tera Systems. "With across-the-board enhancements
 in this release we are further reducing the risks of designing complex,
 multi-million-gate SOCs by enabling faster turnaround times from RTL design to
 GDSII."
     Hiroshi Sakuma, assistant general manager, Technology Foundation Group,
 NEC Electronics said, "TeraForm shows designers how their chips would look in
 silicon without them having to become layout experts. Having verified TeraForm
 on multi-million-gate chips, we observed that when a design processed by
 TeraForm is handed off to NEC, we get a much better starting point, so the
 overall flow is more predictable and unnecessary back-end iterations are
 eliminated."
     With the 2001.1 release of TeraForm, Tera Systems is introducing two new
 package alternatives:  TeraForm-VP for RTL design exploration and TeraForm-EX
 for RTL handoff to logic synthesis and physical layout.
 
     -- TeraForm-VP is an RTL design planning solution that produces a unique
        silicon virtual prototype for analyzing the designer's RTL to determine
        how the micro-architecture affects full-chip, critical-path timing and
        physical layout. Unlike gate-level implementation approaches, TeraForm-
        VP enables the earliest and most accurate reporting of chip area and
        speed and identifies RTL code fragments that would cause downstream
        timing and layout congestion problems.
     -- TeraForm-EX converts the TeraForm-VP virtual prototype into
        industry-standard command and constraint interface files. This gives
        existing third-party logic synthesis and place-and-route tools a better
        starting point, enabling them to achieve rapid timing convergence with
        fewer iterations.
 
     Previously these two packages were part of a single TeraForm-SOC product.
 Decoupling the capabilities results in significant cost savings for Tera
 customers. Both TeraForm-VP and TeraForm-EX are about half the cost of the
 previous TeraForm-SOC product, and typically customers will use multiple VP
 licenses while only needing to purchase a few EX licenses. Libraries and
 design flows for TeraForm-VP and TeraForm-EX are already available for leading
 ASIC vendors, including Fujitsu, LSI Logic and NEC.
     "The new TeraForm-VP processes multi-million-gate chips in hours instead
 of days and gives designers a view of their whole chip instead of just a
 block," said Richard Gordon, executive vice president of Tera Systems.  "Using
 TeraForm before logic synthesis, systems designers can pinpoint critical path
 and floorplan problems and fix the offending RTL before committing their
 design to a gate-level implementation."
 
     New in TeraForm 2001.1
 
     -- New support for the industry-standard VHDL language
     -- Expanded support for Synopsys Design Compiler timing constraints and
        improved sizing and buffer insertion, which results in optimal
        constraints for gate-level synthesis tools and faster timing
        convergence
     -- Automatic chip-level partitioning that minimizes top-level block
        interconnects for improved chip timing performance
     -- Improvements to the optional TeraPath(R) automatic datapath extraction
        and floorplanning algorithms, including stacking, ordering and folding
        that improves datapath density, routability and porosity
     -- A new timing-driven automatic block placement algorithm that can
        rapidly place hundreds of memory and IP macros automatically and
        produce floorplans that are more easily routable by gate-level layout
        tools. In addition, automatic floorplanning capabilities for topology
        shaping, I/O placement and pin assignment have all undergone
        improvements for speed and quality of results
     -- New support for the de-facto industry standard Synopsys .lib and
        Cadence LEF/DEF interface formats
     -- Interfaces to formal verification tools from Synopsys and Verplex
 
     Pricing and Availability
     TeraForm-VP and TeraForm-EX are now shipping, with pricing for each
 starting at $70,000 for a one-year license. For more information, please
 contact Tera Systems at 408-879-1990 or via e-mail at sales@terasystems.com.
 
     About Tera Systems, Inc.
     Tera Systems, Inc., headquartered in Campbell, Calif., is the technology
 leader in RTL design planning solutions for deep submicron system-on-chip
 design. Used by ASIC designers and semiconductor manufacturers, Tera Systems'
 front-end design-creation products ensure back-end design convergence and
 superior chip performance. Tera Systems partners with leading ASIC vendors to
 provide an advanced RTL signoff methodology for next-generation design. For
 more information visit the company's Web site at www.terasystems.com.
 
                      MAKE YOUR OPINION COUNT - Click Here
                http://tbutton.prnewswire.com/prn/11690X86932841
 
 

SOURCE Tera Systems, Inc.
    CAMPBELL, Calif., April 30 /PRNewswire/ -- Tera Systems, Inc., today
 announced a major upgrade to its TeraForm(R) RTL design planning solution,
 TeraForm 2001.1. Enhancements to the TeraForm analysis partitioning,
 floorplanning and timing-optimization capabilities solidify the product's
 status as the new front-end to today's gate-level, logic synthesis and layout
 solutions for high-performance system-on-chip (SOC) design.
     TeraForm is the first tool of its kind to give chip designers essential
 visibility and control over their chip's logical, physical and timing domains
 well ahead of gate-level synthesis and layout. Unlike other EDA approaches
 that require logic designers to learn how to do physical layout, TeraForm
 enables logic designers to focus on register-transfer level (RTL) design
 creation and optimization and then to hand-off a superior design to the
 physical implementation team. By producing a better starting point for
 existing gate-level synthesis and layout tools, TeraForm enables faster
 downstream design convergence with fewer iterations late in the design cycle.
     "Our customers -- both ASIC designers and vendors -- have seen the value
 of TeraForm across numerous SOC designs since we first introduced it in 1998,"
 said Tommy Eng, president of Tera Systems. "With across-the-board enhancements
 in this release we are further reducing the risks of designing complex,
 multi-million-gate SOCs by enabling faster turnaround times from RTL design to
 GDSII."
     Hiroshi Sakuma, assistant general manager, Technology Foundation Group,
 NEC Electronics said, "TeraForm shows designers how their chips would look in
 silicon without them having to become layout experts. Having verified TeraForm
 on multi-million-gate chips, we observed that when a design processed by
 TeraForm is handed off to NEC, we get a much better starting point, so the
 overall flow is more predictable and unnecessary back-end iterations are
 eliminated."
     With the 2001.1 release of TeraForm, Tera Systems is introducing two new
 package alternatives:  TeraForm-VP for RTL design exploration and TeraForm-EX
 for RTL handoff to logic synthesis and physical layout.
 
     -- TeraForm-VP is an RTL design planning solution that produces a unique
        silicon virtual prototype for analyzing the designer's RTL to determine
        how the micro-architecture affects full-chip, critical-path timing and
        physical layout. Unlike gate-level implementation approaches, TeraForm-
        VP enables the earliest and most accurate reporting of chip area and
        speed and identifies RTL code fragments that would cause downstream
        timing and layout congestion problems.
     -- TeraForm-EX converts the TeraForm-VP virtual prototype into
        industry-standard command and constraint interface files. This gives
        existing third-party logic synthesis and place-and-route tools a better
        starting point, enabling them to achieve rapid timing convergence with
        fewer iterations.
 
     Previously these two packages were part of a single TeraForm-SOC product.
 Decoupling the capabilities results in significant cost savings for Tera
 customers. Both TeraForm-VP and TeraForm-EX are about half the cost of the
 previous TeraForm-SOC product, and typically customers will use multiple VP
 licenses while only needing to purchase a few EX licenses. Libraries and
 design flows for TeraForm-VP and TeraForm-EX are already available for leading
 ASIC vendors, including Fujitsu, LSI Logic and NEC.
     "The new TeraForm-VP processes multi-million-gate chips in hours instead
 of days and gives designers a view of their whole chip instead of just a
 block," said Richard Gordon, executive vice president of Tera Systems.  "Using
 TeraForm before logic synthesis, systems designers can pinpoint critical path
 and floorplan problems and fix the offending RTL before committing their
 design to a gate-level implementation."
 
     New in TeraForm 2001.1
 
     -- New support for the industry-standard VHDL language
     -- Expanded support for Synopsys Design Compiler timing constraints and
        improved sizing and buffer insertion, which results in optimal
        constraints for gate-level synthesis tools and faster timing
        convergence
     -- Automatic chip-level partitioning that minimizes top-level block
        interconnects for improved chip timing performance
     -- Improvements to the optional TeraPath(R) automatic datapath extraction
        and floorplanning algorithms, including stacking, ordering and folding
        that improves datapath density, routability and porosity
     -- A new timing-driven automatic block placement algorithm that can
        rapidly place hundreds of memory and IP macros automatically and
        produce floorplans that are more easily routable by gate-level layout
        tools. In addition, automatic floorplanning capabilities for topology
        shaping, I/O placement and pin assignment have all undergone
        improvements for speed and quality of results
     -- New support for the de-facto industry standard Synopsys .lib and
        Cadence LEF/DEF interface formats
     -- Interfaces to formal verification tools from Synopsys and Verplex
 
     Pricing and Availability
     TeraForm-VP and TeraForm-EX are now shipping, with pricing for each
 starting at $70,000 for a one-year license. For more information, please
 contact Tera Systems at 408-879-1990 or via e-mail at sales@terasystems.com.
 
     About Tera Systems, Inc.
     Tera Systems, Inc., headquartered in Campbell, Calif., is the technology
 leader in RTL design planning solutions for deep submicron system-on-chip
 design. Used by ASIC designers and semiconductor manufacturers, Tera Systems'
 front-end design-creation products ensure back-end design convergence and
 superior chip performance. Tera Systems partners with leading ASIC vendors to
 provide an advanced RTL signoff methodology for next-generation design. For
 more information visit the company's Web site at www.terasystems.com.
 
                      MAKE YOUR OPINION COUNT - Click Here
                http://tbutton.prnewswire.com/prn/11690X86932841
 
 SOURCE  Tera Systems, Inc.