SAN FRANCISCO, Feb. 22, 2011 /PRNewswire/ -- Texas Instruments Incorporated (TI) (NYSE: TXN) and the Massachusetts Institute of Technology (MIT) today presented a joint research paper detailing design methodologies for a 28-nanometer (nm) mobile applications processor at the 2011 International Solid-State Circuits Conference (ISSCC). The paper—"A 28nm 0.6V Low Power Digital Signal Processor (DSP) for Mobile Applications"—demonstrates that a DSP is capable of scaling from high-performance mode at 1.0 volts down to an ultra-low power (ULP) mode at 0.6 volts (V). This DSP is one of the first system-level, low voltage, 28nm designs for the mobile device market, demonstrating TI's continued commitment to enabling lower power and extended battery life in mobile devices running advanced applications.
"As the multimedia and computing capabilities of TI's OMAP™ platform-based smartphones, tablets and other mobile devices increase, there is a continually expanding gap between performance demands and battery capacity," said Gordon Gammie, Distinguished Member of the Technical Staff at TI and ISSCC presenter. "TI believes that 28nm process technology advancements, developed in tandem with TI and MIT's low power circuit and methodology collaboration, gives us the right knowledge base to successfully meet the next-generation processing demands within the future mobile power envelope."
High performance and Ultra-Low Voltage (ULV) designs present several challenges. Two of the most prominent are low-voltage functionality and timing closure in the face of process variations without sacrificing high-voltage performance at nominal voltage. To address these challenges, TI and MIT successfully developed these two key methodologies:
Ultra-low voltage circuits: At low voltages in deep submicron process nodes, within-die random variation in transistor threshold voltage can cause circuits to have functional failures. A standard cell library and custom low-voltage memory using novel ULV design methodologies are developed to be robust at 0.6V.
Statistical Static Timing Analysis (SSTA) at low voltage: The delay distribution of standard cells at low voltages is no longer a Gaussian random variable. Traditional SSTA tools based on a Gaussian distribution can suffer from 10-70 percent underestimation of delay at 0.6V. A newly developed SSTA technique has been shown to improve the accuracy of design timing at ULV to less than eight percent. The ability to accurately analyze low-voltage timing avoids excessive design margins and minimizes impact to area and high-voltage performance.
"The design of a low-voltage processor in 28nm requires a system-level approach – from optimizing the circuit styles and memories to the development of a custom low-voltage timing flow," said Anantha Chandrakasan, MIT professor and pioneer in the area of low-power design. "This chip demonstrates an aggressive low-power methodology to ensure robust low-voltage and ultra-low-power operation for a smartphone application processor."
TI's 0.6 V ULP DSP presented in this paper was designed by a team of MIT students and TI engineers, and is an extension of a long-standing joint relationship on low power and ultra-low power research.
"This is an excellent example of the results that come from a long and fruitful collaboration between a university and corporation such as MIT and Texas Instruments," said Gene Frantz, Principal Fellow at TI. "The students benefit by demonstrating their innovations on complex, DSPs with several million transistors made in state-of-the-art CMOS. TI and its customers benefit from early access to the students' innovations."
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