TRUECHIP ANNOUNCES EARLY ADOPTER VERSION OF SUB-SYSTEM VERIFICATION IP

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Feb 27, 2023, 22:41 ET

SAN JOSE, Calif. and BENGALURU, India, Feb. 28, 2023 /PRNewswire/ -- Truechip, the Verification IP Specialist, announced that it has launched an early adopter version of Sub-system Verification IP (SS VIP). A sub-system level verification reduces the verification cycle time as it requires much lesser run time compared to SOC Verification. A sub-system typically involves multiple related IP functions, each of which may be independent small or large protocols. These related IP functions combine to perform a new function, in a way that fulfills the sub-system requirement of the chip architect and may be suitable to a wide range of applications such as Artificial intelligence, Defense, Personal computing, Data centers, Networking and healthcare industry to name a few.

Speaking at DVCON US, held at San Jose, California, Nitin Kishore, CEO, Truechip, said, "The launch of Sub-System Verification IP is another step towards macro level verification. Last year we came up with NoC Verification IP which helps to automate the verification of any NoC DUT. Verification engineers can take advantage of this Sub-System VIP not only to reduce the verification cycle time but also to use their creativity at a higher abstraction level. This Sub-System VIP can help to create automated testbench around the DUT, integrate the VIPs automatically and also create test cases to verify the DUT."

Mr. Kishore further added, "This Sub-System Verification IP is aimed to significantly reduce Customer's time to market, verification cycle time and cost by automation and breakthrough solutions, thereby enabling advancement of next gen chips."

TruEye Sub-System Verification IP Key Features:

Sub-System Memory Map: User will provide the memory map information of the Sub-system DUT to the GUI, along with tasks/ sequences to configure the peripherals.
Sub-System Verification can be done to verify only connectivity checks or full coverage verification
Sub-System may contain one or more masters to initiate the transactions along with a NoC/ Crossbar or Fabric
Sub-System may contain multiple peripherals for which VIPs will be automatically integrated and test cases will also be generated.
Sub-System Performance requirements are checked and summary is shared with the user.
Automated Regression and Regression Analysis are also provided.
Register Verification of Sub-system will also be performed by the Sub-System Verification IP.

Speaking on the occasion, Saurabh Agarwal, Head-Marketing & Sales at Truechip, said, "Continuous evolvement has been a center of our working strategy. With such a rich heritage, world-class delivery and emphasis on client service, we will always embody a spirit of flexibility and commitment to being a true partner, in the trenches with our clients every step of the way. Truechip's commitment to innovation, precision extends to software-driven insights and analytics that bring tomorrow's technology products to market faster across the development lifecycle, in design and verification IPs, automated GUI solutions and Silicon IP to organizations."

For more information on Sub-system Verification and any other VIPs, visit our website or can click here.

About Truechip:

Truechip is a leading provider of Verification IPs, NOC Silicon IP, GUI based automation products and chip design services, which aid to accelerate IP/ SOC design thus lowering the cost and the risks associated with the development of ASIC, FPGA and SOC. Truechip provides Verification IP solutions for RISC V-based chips, Networking, Automotive, Microcontroller, Mobile, Storage, Data Centers, AI domains for all known protocols along with custom VIP development. The company has global footprints and coverage across North America, Europe, Israel, Taiwan, South Korea, Japan, Vietnam and India. Truechip offers Industry's first 24 x 7 technical support.