Professor Horowitz of Stanford University Recognized with ACM/IEEE CS Eckert-Mauchly Award

The Eckert-Mauchly Award is widely known as the computer architecture community's most prestigious award. 

LOS ALAMITOS, Calif., June 16, 2022 /PRNewswire/ -- The IEEE Computer Society (IEEE CS) and the Association for Computing Machinery (ACM) have named Professor Mark Horowitz as the 2022 recipient of the ACM/IEEE CS Eckert-Mauchly Award.  An IEEE and ACM Fellow, Horowitz is a professor with a joint appointment in the Departments of Electrical Engineering and Computer Science at Stanford University, and is being recognized "for contributions to microprocessor memory systems." 

Prof. Horowitz has made numerous contributions to computer architecture and to the architecture of computer memory systems. Highlights of his accomplishments include:

• He was one of the first to identify the processor-DRAM interface as a key bottleneck that required architecture and circuit optimization. With Mike Farmwald he pioneered high-bandwidth DRAM interfaces. Modern DRAM interfaces such as SDDR and LPDDR were strongly influenced by his techniques.
• His deep insights at the intersection of architecture and circuits have profoundly influenced the field. He demonstrated the growing importance of wire delay in systems and large memories through his landmark paper, "The Future of Wires" in 2001. He also foresaw the eventual end of Dennard Scaling and was an early champion of the importance of energy efficiency in processors. As a result, he has led research on different approaches for achieving efficiency and predicted the rise of hardware accelerators. 
• He pioneered work in Smart Memories, realizing that sometimes adding a little functionality to a memory can greatly improve an application's energy efficiency. Many of today's domain-specific architectures build on this concept.

During the 1980s, Horowitz developed quantitative methods for optimizing emerging microprocessor cache memory systems. While it is hard to imagine now, during that period it was not possible to generated memory traces that included the operating system. He worked with Anant Agarwal and Dick Sites to develop ATUM, a tool that, for the first time, enabled the collection of large address traces which included the operating system and multiprogramming effects. Using this data allowed them to create a much more accurate analytical cache model. Using the insights gained from these tools, he developed MIPS-X, the first processor with an on-chip instruction cache. He then extended this work to develop performance-optimal multi-level cache hierarchies with Steven Przybylski. The work that Prof. Horowitz did in the 1980s led to the multi-level, on-chip cache architecture that is found in almost every computer today.

Horowitz co-founded Rambus in 1990 with Mark Farmwald to pioneer high-bandwidth DRAM interfaces. This work was the first to identify future systems would need fewer DRAM chips, but more memory bandwidth, which meant that the DRAM chip interface was the key bottleneck that required architecture and circuit optimization. Modern DRAM interfaces such as SDDR and LPDDR were strongly influenced by many of the techniques pioneered by Rambus. Horowitz, with his colleagues at Rambus and his students at Stanford, also developed much of the signaling technology found in today's modern high-bandwidth memory interfaces.

Parallelism is another avenue for processor efficiency, but that raised the question of how to keep caches consistent in large machines. In the 1990s, Horowitz was also a major contributor to the DASH and FLASH projects, which explored scalable methods for implementing cache coherency using directories rather than snooping protocols. Today almost all cache-coherent multiprocessors rely on such directory mechanisms either within or across multicores.

Horowitz's contributions always build on a deep and strong understanding of CMOS circuits. His landmark paper with Ron Ho, "The Future of Wires," published in 2001, shows the growing importance of wire delay in all systems and particularly in large memories. These insights led to the Smart Memories design, which employed local memories placed with processor tiles, avoiding long wires. Smart Memories demonstrated that it was possible to configure memory as well as processors in a machine and was the first to support distributed shared memory as well as transactional memory. Several of the new domain-specific architectures rely on structures pioneered in the Smart Memories project.

There is no individual who has had a larger influence on the memory architecture of modern computers. A modern multi-core processor has multiple SDDR memory channels – a legacy of Horowitz's work at Rambus and using many circuit techniques he developed. The same processor has a multi-level on-chip cache hierarchy based on the architecture and designs that Horowitz pioneered in the 1980s. 

Horowitz will receive the Eckert-Mauchly Award during the ACM/IEEE International Symposium on Computer Architecture (ISCA), to be held in New York City, June 18^t – 22. The Eckert Mauchly Award will be presented on June 21. 

The Eckert-Mauchly Award was initiated in 1979 and comes with a US $5,000 prize. The award was named for John Presper Eckert and John William Mauchly, who collaborated on the design and construction of the Electronic Numerical Integrator and Computer (ENIAC), the pioneering large-scale electronic computing machine that was completed in 1947.

The IEEE Computer Society is the world's home for computer science, engineering, and technology. A global leader in providing access to computer science research, analysis, and information, the IEEE Computer Society offers a comprehensive array of unmatched products, services, and opportunities for individuals at all stages of their professional careers. Known as the premier organization that empowers the people who drive technology, the IEEE Computer Society offers unparalleled international conferences, peer-reviewed publications, a unique digital library, and training programs. Visit www.computer.org for more information. 

SOURCE IEEE Computer Society