NEW YORK, Jan. 3, 2013 /PRNewswire/ -- Reportlinker.com announces that a new market research report is available in its catalogue:A Magnetic Moment: Prospects for MRAM Technology, Markets and Applications
Current charge-based semiconductor storage technologies such as SRAM, DRAM, NOR flash and NAND flash face scaling challenges as geometries shrink below 20nm. As a result, a marked increase in research activity focused on alternative memory technologies has occurred over the last decade.
Non-charge storage-based memories such as FeRAM and MRAM offer fast RAM-like performance along with non-volatility and extremely high endurance. Although in commercial production, both suffer from high costs vis-à-vis current technologies and have only been able to address niche applications.
All that is likely to change with the availability of samples of in-plane spin-torque transfer MRAM (STT-MRAM) from Avalanche Technology and Everspin Technologies. These achievements are a stepping stone to next generation perpendicular STT-MRAM which promises a scalable path with the potential to broaden its appeal into mainstream consumer applications. As a consequence, the embedded and standalone non-volatile RAM markets are on the cusp of explosive growth in the next few years.
A Magnetic Moment: Prospects for MRAM Technology, Markets and Applications offers an independent view of the opportunities and challenges presented by MRAM technology and its potential as one of the leading contenders in the emerging memory space.Table of Contents
ContentsList of FiguresList of TablesExecutive SummaryMemory OverviewIntroductionThe Memory HierarchySRAMConceptTechnology EvolutionDRAMConceptTechnology EvolutionNOR FlashConceptTechnology EvolutionNAND FlashConceptTechnology EvolutionFerroelectric MemoriesFerroelectric Random Access Memory (FeRAM)Ferroelectric Transistors (FeFET)Phase Change MemoryConceptBasic OperationOther Resistive Switching MemoriesMRAMIntroductionConventional DesignToggle MRAMConceptMaterials for the Toggle-MRAM:Thermal Assisted Switching TAS-MRAMConceptMaterials for the TAS-MRAMSpin-Transfer Torque (STT) MRAMConceptMaterials for the STTThermal Stability and RetentionWrite Margin vs. ReliabilityScalabilityMaterials with Perpendicular Magnetic Anisotropy (PMA)Domain wall (DW) motion MRAMConceptMaterials for the DW-Motion MRAM CellIncreasing the Bit Density With Multi Level Cells (MLC)MLC Based on Single MTJsMLC Based on Parallel Connected MTJsMLC Based on Series Connected MTJsMLC Based on Domain Wall MotionMLC ProgrammingTwo-Step ProgrammingProbabilistic ProgrammingDesign and ArchitectureSTT-MRAM Cell Design1T-1MTJ2T-1MTJShared Source-Line (-Plane)Selection DeviceSensing SchemesData Retention RelaxationRacetrack MemoryMTJ in non-volatile logicIntroductionNon-volatile Latch/Flip-FlopNon-volatile AdderNon-volatile Look-up Table (LUT)Spin-logicMRAM FabricationProcess flowElement shape3D IntegrationMRAM Cost DriversProcess ComplexityCell EfficiencyYieldCost per BitMemory ComparisonMRAM CharacteristicsSwitching TimeCurrent / Power ConsumptionRetention TimeEndurance and Wear LevelingECCScalingMRAM vs. DRAMMRAM vs. FlashMRAM vs. SRAMMRAM vs. FeRAMMRAM vs. PCMRoadmapMRAM StatusAeroflex, Inc.Avalanche TechnologyCrocus TechnologyEverspin Technologies, Inc.Freescale SemiconductorHitachi Ltd.Honeywell International, Inc.IBM Corp.Infineon Technologies AGIntel Corp.Magsil CorporationMicromem Technologies, Inc.Micron TechnologyNEC Corp.NVE Corp.Qualcomm, Inc.Renesas TechnologySamsung ElectronicsSK Hynix SemiconductorSpin Transfer TechnologiesSpingate Technology LLCSPINTECST MicroelectronicsTaiwan Semiconductor Manufacturing CompanyToshiba Corp.Tower Semiconductor Ltd.Market and ApplicationsIntroductionEmbedded MRAM MarketRequirement For Successful eMRAM Market EntryProcessor Companion Devices with Battery-backed SRAM and Real-time ClockSet-top box MCU using EEPROM or Battery-Backed SRAMRF ID Devices, Smartcards, and e-PassportsSmart MetersMobile Baseband SOCsMobile Application Processor SoCsEmbedded nvRAM Market ForecastBB-SRAMFERAMnvSRAMMRAMMarket for nvRAM Product Revenue by TechnologyEmbedded MRAM Market and Applications OutlookStandalone MRAM MarketMemory Market Segmentation Based Upon Price/Bit and Feature Sets DifferentiationMRAM as an SRAM ReplacementMRAM as a Non-volatile RAMRAID Write Index ApplicationSmartMeter Datalog ApplicationOther nvRAM ApplicationsMRAM as a DRAM ReplacementHigh Density DRAM-compatible MRAM ApplicationsInstant-on Embedded Controller MemoryRAID Non-volatile Cache MemoryHDD Non-volatile Buffer MemoryEnterprise SSD Metadata Cache/BufferMobile Chipset MemoryMRAM as a Storage Class MemoryStandalone MRAM Market and Applications SummaryReferencesAbout the AuthorsAbout Forward InsightsServicesContactAbout NamLabContactList of Figures
Figure 1. Memory HierarchyFigure 2. SRAM Cell SchematicFigure 3. Monolithic 3D SRAM TechnologyFigure 4. DRAM Cell SchematicFigure 5. DRAM Cell Transistor EvolutionFigure 6. DRAM Cell Capacitor TrendFigure 7. NOR Flash Cell (ETOX: EPROM thin oxide cell)Figure 8. NOR ArchitectureFigure 9. NOR Flash CellFigure 10. NOR Flash Technology EvolutionFigure 11. Drain Bias MarginFigure 12. Multi-bit Charge Trapping CellFigure 13. NAND ArchitectureFigure 14. NAND Cell StringFigure 15. NAND Flash Technology EvolutionFigure 16. NAND Flash Memory Gap Fill at 63nm and Flat Memory Cell at 20nmFigure 17. Electrons Stored on the Floating GateFigure 18. Operation of a FeRAM MemoryFigure 19. Ferroelectric Field Effect TransistorFigure 20. Basic PCM Cell Structure and Cell OperationFigure 21. Resistive Switching EffectsFigure 22. MRAM-Cell RequirementsFigure 23. Schematic View of (a) Field-Induced Switching MRAM and (b) STT MRAM.Figure 24. MRAM Operation with Field-Induced SwitchingFigure 25. Switching Field Threshold for Permalloy Magnetic Elements of Different Ends.Figure 26. Program Operation in the Toggle Switching Scheme MRAM DesignFigure 27. Toggle-MRAM Cell with a Select TransistorFigure 28. MTJ Layer Stack and the Uniformity RequirementsFigure 29. Writing Procedure for (a) a Conventional MRAM Cell and (b) TAS MRAM CellFigure 30. MTJ Design for a) Conventional Field Driven Approach and b) TAS ApproachFigure 31. Architecture of a TAS-MRAM Memory ArrayFigure 32. Influence of the Thickness of an IrMn Layer on the Exchange Bias FieldFigure 33. Area Dependency of the Write Power for a TAS-MRAM CellFigure 34. TAS-MRAM Cell Material Stack and Write Power Density vs. Junction AreaFigure 35. Material Stack for a Double Barrier MTJ with one Thermal BarrierFigure 36. Spin Torque Transfer MRAM ConceptFigure 37. Schematic View of a Typical STT Memory Element and TEM Cross-SectionFigure 38. Illustration of the Spin Polarization Enhancement for a Dual Barrier StructureFigure 39. Normalized Switching Current Thresholds vs. Magneto-Resistance RatioFigure 40. STT-MRAM Write Current Scaling for Different MTJ StructuresFigure 41. Required Room Temperature Values for ?HFigure 42. Calculated Single Bit Cycle to Cycle Read Error Rate for three ?I ValuesFigure 43. Measured Critical Switching Voltage and Break Down Voltage DistributionsFigure 44. Switching Probability vs. Switching Pulse WidthFigure 45. BER Curves Showing a Bifurcated Switching,Figure 46. Planar MTJ Scaling: Thickness and Switching Current Density vs. Cell WidthFigure 47. Comparison of (a) In-Plane STT-MRAM and (b) Perpendicular STT-MRAM.Figure 48. Illustration of Perpendicular STT-MRAM DesignFigure 49. Scaling of Critical Switching Current for In-Plane and Perpend. MTJ ElementsFigure 50. Possible Cell Structure and Operation Principle of the DW-Motion MRAM CellFigure 51. DW-Motion Cell Structure a) and Cross-Sectional TEM Image b)Figure 52. DW-Motion Velocity in a Co/Ni Nano-Laminate Free LayerFigure 53. MLC in Single MTJs - Calculated TMR RatioFigure 54. Schematic Illustration of MLC-MTJFigure 55. MLC STT-MRAM Cell with Series Connected MTJsFigure 56. Stacked MTJ Cell Fabrication and Bit Cost ScalingFigure 57. MLC with Field Compensation LayerFigure 58. Schematic Representation of MLC Cell Based on Domain Wall MotionFigure 59. State Transition Graphs of Write SchemesFigure 60. Probabilistic ProgrammingFigure 61. 1T-1MTJ STT-MRAM StructureFigure 62. 2T1MTJ Structure and LayoutFigure 63. Shared SourceLine: a) Schematic and b) LayoutFigure 64. MTJ Current Scaling Compared to the Current Scaling of Select DevicesFigure 65. Non-Destructive Self-Reference Sensing Scheme:Figure 66. Comparison of Different MTJ Designs at 350K:Figure 67. Magnetic Racetrack Memory – a 3D Shift RegisterFigure 68. The Circuit Diagram of Non-volatile Latch Fabricated by NECFigure 69. The Circuit Diagram of Non-volatile Latch Designed by STMicroelectonicsFigure 70. Non-volatile Adder Fabricated by Hitachi.Figure 71. Non-volatile Lookup-Table Fabricated by HitcathiFigure 72. Schematic of Programmable Spin-LogicFigure 73. MRAM Sputtering Cluster ToolsFigure 74. Schematic Cross Sectional View of an MRAM Module in the Back End Of LineFigure 75. SEM Cross Section of CMOS Chip with Back End Of Line MTJ MRAMFigure 76. Top view of MTJ, TEM Cross-Section and Key Process Flow of STT-MRAMFigure 77. Cross Section of 4Mb MRAM Product and Top-View of the Tunnel JunctionFigure 78. Trade-Off Between Operating Time and Writing Current of the STT-MTJFigure 79. Operation of the Proposed Lookback SchemeFigure 80. Block Diagram of a Cache With Lookback SchemeFigure 81. Minimum ? (Thermal Stability) Required to Get a 10 Year MTTF.Figure 82. The Dual-ECC Memory Architecture with Intrinsic and Extrinsic ECCs.Figure 83. Cell Size TrendFigure 84. Memory Density TrendFigure 85. MRAM Papers Presented at VLSI Symposium and IEDMFigure 86. Everspin 64Mb ST-MRAM Die PhotoFigure 87. 54nm STT-MRAMFigure 88. OST-MRAM vs. Conventional MRAMFigure 89. Spingate's Roadmap and Target MarketFigure 90. Re-write Current Density and MR RatioFigure 91. 30-Nanometer Diameter MTJFigure 92. Crocus-TowerJazz TAS- MRAMFigure 93. Device CharacteristicsFigure 94. eFlash and NOR Flash Memory MarketFigure 95. MRAM as Converged Embedded MemoryFigure 96. Toggle Mode MRAM Uses Higher Write Power to Generate Magnetic FieldsFigure 97. Spin Torque MRAM Directly Switches MTJ Using Current Through CellFigure 98. Cubic Corporation GoCard used eFERAM RF ID ChipFigure 99. Processor with Hybrid Cache MemoryFigure 100. Market for Embedded nvRAM Products by TechnologyFigure 101. Embedded MRAM Value by Application SegmentFigure 102. Standalone Memory MarketFigure 103. Memory Price per MB TrendsFigure 104. Volatile Memory PyramidFigure 105. Non-volatile Memory PyramidFigure 106. SRAM MarketFigure 107. Battery-Backed SRAM and nvSRAMFigure 108. RAID Disk Controller Showing RAID Write Journal and Cache MemoriesFigure 109. Comparison of HDD Recording MethodsFigure 110. Buffalo's SSD with MRAM cacheFigure 111. Concept of Storage Class MemoryFigure 113. Price per Megabyte Trend of Conventional and Emerging Memory TechnologiesFigure 114. nvRAM Market ForecastFigure 115. Standalone MRAM Market by Application SegmentList of Tables
Table 1. Comparison of In-Plane and Perpendicular MTJTable 2. Comparison of Conventional CMOS Adder and the Non-volatile AdderTable 3. Estimated Process Complexity for a STT-MRAM ManufacturingTable 4. Relative Cost Estimation for STT-MRAM Compared to DRAM and NAND FlashTable 5. Memory ComparisonTable 6. Embedded Memory RoadmapTable 7. Standalone Memory RoadmapTable 8. Spingate's ps-MRAM vs. Other Memory TechnologiesTable 9. Key Parameters for eNVM ApplicationsTable 10. Market for Embedded nvRAM Products by TechnologyTable 11. Embedded MRAM Technology and Applications RoadmapTable 12. Embedded MRAM Revenue and Units by ApplicationTable 13. Standalone MRAM Technology, Density and Applications RoadmapTable 14. Price per Megabyte Trend of Conventional and Emerging Memory TechnologiesTable 15. Detailed MRAM Forecast (Revenue & Units)
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