Altos New 3.1 Version Speeds IP Characterization Throughput by 2-3X

CAMPBELL, Calif., April 5, 2011 /PRNewswire/ -- Altos Design Automation, Inc. today announced new versions of their industry-leading IP characterization products, Liberate and Variety, that improve throughput by a factor of 2-3X. The new 3.1 version employs a distributed processing "packet" technology that packages cell characterization simulations together and submits them to a job-distribution queue as a single process. By optimizing the size of these cell packets, job queuing overhead is greatly reduced, optimizing the use of multi-CPU cores that use shared memory. Throughput is further improved by enabling multi-threading for the simulations within each packet, conserving both memory and CPU resources for each machine. Multiple distinct packets utilize all available memory and CPU threads simultaneously, resulting in a highly efficient usage of compute resources and providing up to 3X improvement in throughput. The new packet method is particularly well-suited to the large cell libraries used by leading IP providers, foundries and semi-conductor firms that may contain as many as 6,000 cells.

"Previously distributed modes for cell characterization were either at the library or cell level. As library sizes have increased, library-level distribution has become too large, while cell-level distribution is too small for all but the largest cells due to the job queue overhead", said Altos CTO and founder, Ken Tseng. "By creating an intermediate layer of granularity or "packet" we have optimized the library characterization problem to best suit today's compute farm environments that typically comprise hundreds of multi-CPU machines managed by a job queuing system. We have also been able to parallelize much of the sequential processing that is performed prior to simulation such as automatic vector generation, so that each "packet" is an autonomous process with a small memory footprint. One of our leading foundry customers has reported 2.5X improvement in turnaround time on a commercial library of ~1,500 cells while another of our leading fab-less customers has reported >3X improvement for a 4,000 cell library."

Altos' CEO and founder, Jim McCanny added, "Altos is continuing to raise the bar in optimizing characterization performance. In addition to improved turn around time, the 3.1 release adds support for additional third party simulators, improves IBIS support for complex I/O cells such as DDR2 and DDR3 that feature on-die termination (ODT), and offers the ability to use distinct process models for leakage characterization."

About Liberate

Liberate is an ultra-fast library creator that generates electrical models in Liberty®, Verilog, Vital and IBIS formats. Liberate supports all the latest models for timing, noise and power such as CCS (Composite Current Source) and ECSM (Effective Current Source Models)  Liberate also supports ultra low power and high speed design styles that include power gating cells, state retention registers, level shifters, pulse clocking and CML.

About Variety

Variety creates SSTA models for PrimeTime VX, Extreme GoldTime and Cadence ETS that include the impact of process parameter variations.  All library timing data is characterized for variation including delays, transitions, timing constraints and pin capacitances. Both linear and non-linear models can be created as well as driver and receiver current source models, both Composite Current Source (CCS) and Effective Current Source Models (ECSM) are supported.  Variety can characterize for both global (systematic) and local (random) variation. Variety also create AOCV (Advanced On Chip Variation) tables to support non-statistical timing flows .

About Altos

Altos Design Automation provides ultra-fast, fully-automated characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization.  Altos advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield.

Privately held, Altos was founded in 2005 in Santa Clara, CA.  Its corporate headquarters is at 1919 South Bascom Ave., Suite 250, Campbell, CA 95008. Telephone: (408) 980-8056. On the Web at: http://www.altos-da.com

For more information contact:

Jim McCanny
Altos Design Automation, Inc.
[email protected]
408-980-8056

Liz Massingill
Lee PR
[email protected]
650-363-0142

SOURCE Altos Design Automation Inc.