Amlogic Reduces HW/SW Integration Time for Multimedia SoCs by Two Months Using the Cadence Protium S1 FPGA-Based Prototyping Platform
Apr 26, 2017, 10:45 ET
Fast prototype bring-up and congruency with Palladium Z1 Enterprise Emulation Platform enable early software development
SAN JOSE, Calif., April 26, 2017 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Amlogic has adopted the new Cadence® Protium™ S1 FPGA-Based Prototyping Platform to deliver multimedia system-on-chip (SoC) designs to market faster. Using the Protium S1 platform, Amlogic accelerated its hardware/software (HW/SW) integration process, resulting in a time savings of two months compared to its previous traditional HW/SW integration method. For more information on the new Protium S1 FPGA-Based Prototyping Platform, visit www.cadence.com/go/protiums1.
Amlogic, an early participant in the Protium S1 platform beta program, found that the platform's unique implementation and accelerated time to prototype capabilities enabled its engineering team to begin software development on its SoC designs earlier than before. The platform also allowed designers to boot Linux and Android faster and run AnTuTu benchmark scoring in a single day.
"The Protium S1 platform enabled us to successfully run multiple instances of the design in parallel so that we could be much more productive," said Jerry Cao, software engineering director at Amlogic. "In addition, the platform shares a common compile flow with the Cadence Palladium® Z1 Enterprise Emulation Platform, which allows us to re-use our existing Cadence verification environment and achieve functional congruency between the two platforms."
The Protium S1 FPGA-Based Prototyping Platform is a next-generation platform that enables early software development, reducing design bring-up time by an average of 80 percent versus traditional FPGA prototyping approaches. The Protium S1 platform further extends the innovation within the Cadence Verification Suite and supports the company's System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.
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