Cadence Expands JasperGold Platform for Advanced Formal-Based RTL Signoff

JasperGold Formal Verification Platform's new Superlint and Clock Domain Crossing Apps reduce logic designer's IP development time by up to four weeks

SAN JOSE, Calif., May 16, 2017 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the expansion of its JasperGold^® Formal Verification Platform with the introduction of the JasperGold Superlint and Clock Domain Crossing (CDC) Apps, advanced formal-based technologies that address register-transfer level (RTL) signoff requirements. The Superlint and CDC Apps bring the power of JasperGold formal technology to the RTL designer's desktop. The new apps improve IP design quality by reducing late-stage RTL changes by up to 80 percent and reducing IP development time by up to four weeks when compared to existing verification solutions. For more information on the JasperGold technologies for RTL signoff, please visit www.cadence.com/go/rtlsignoff.

With today's larger, more complex designs, there is a growing need to develop robust IP that can be reused in multiple SoCs to improve designer productivity. Signoff checks that were previously performed at the netlist implementation stage now need to be performed on the RTL design. Traditional static lint and CDC tools have not been effective at ensuring that the RTL code is of the highest quality.

With the delivery of the latest JasperGold formal-based RTL signoff technologies, designers have access to richer functional checks and formal-powered intelligent debugging to reduce violation noise, which is one of the most pressing RTL signoff challenges today. The JasperGold Superlint and CDC Apps are fully integrated with the powerful JasperGold Visualize^™ debug environment, utilizing proven formal intelligence to increase debug efficiency for RTL designs. Additionally, both apps incorporate Cadence's existing formal capabilities to improve waiver handling. Designers can now perform signoff with robust, reusable and CDC-clean RTL code in the verification and implementation phase, shortening overall time to market and significantly improving design quality.

"Ever-increasing project schedule and IP quality pressures make effective RTL signoff an important part of the development process," said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. "Building upon the proven JasperGold platform, Cadence is bringing its industry-leading formal technology to RTL signoff, giving logic designers the ability to develop more robust and reusable IP code in a significantly shorter amount of time."

In the new Superlint App, Cadence has combined traditional RTL linting and formal verification capabilities, deriving the most complete set of functional checks from the RTL automatically. Similarly, the CDC App offers a metastability injection flow for rigorous CDC verification in either the Cadence^® JasperGold formal or Xcelium^™ Parallel Simulator environments for more comprehensive signoff.

Customer Endorsements

"We've been using the JasperGold Superlint App at ARM for more than a year, and we've had success with improving RTL signoff and shortening time to market. With the ability to find bugs weeks earlier in the design process, we've reduced late-stage RTL changes, which enables the team to save additional time when we get to the functional verification stage."
-Hobson Bullman, vice president and general manager, Technology Services Group, ARM

"We've identified functional and structural CDC issues earlier in the RTL signoff phase using the JasperGold CDC App. Eliminating these bugs earlier in the process has increased the quality of our designs and saved us between two and four weeks on the design and verification time for each of our IP."
-David Vincenzoni, Design Manager at STMicroelectronics

The new JasperGold Superlint and CDC Apps for RTL Signoff further extend the innovation within the Cadence Verification Suite. The new apps also support the company's broader System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

About Cadence
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company's System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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SOURCE Cadence Design Systems, Inc.

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