Cadence: Leading the EDA Industry with AI-Powered Platforms

TAIPEI, Jan. 8, 2025 /PRNewswire/ -- The increasing penetration of artificial intelligence (AI) functions in many applications is driving greater complexities in chip designs and architecture. Couple this with the ever-growing focus on power, performance, and area (PPA) considerations, chip designers are now facing increasing challenges in developing smaller, faster, and lower-power devices, in more and more advanced nodes.

One challenge on this front is power integrity. At advanced nodes, designers regularly face a significant number of EM-IR violations at signoff, thereby making it imperative to address this challenge early in the design phase.

However, one major bottleneck of in-design EM-IR analysis is that it is computationally very expensive due to the size and coupled nature of the power network.

Therein lies the rub. To address these design problems in creating devices that will support increasingly complex functions with more intelligence, especially AI, one must then resort to AI at the earliest phase of the design stage.

That's what Cadence did by releasing Voltus InsightAI, the industry's first generative AI technology that automatically identifies the root cause of EM-IR drop violations early in the design process and selects and implements the most efficient fixes to improve PPA. Using Voltus InsightAI, customers can fix up to 95% of violations prior to signoff, leading to a 2X productivity improvement in EM-IR closure.

"Voltus InsightAI is the industry's first EDA product that uses AI to effectively predict root cause and resolve IR drop issues in the design implementation phase," says Albert Zeng, Sr. Software Engineering Group Director in the System Design and Analysis Group at Cadence, during an interview with EE Times Asia. "It uses AI technology to decide on the most efficient ways to improve the design and uses AI models for faster IR inferencing in order to provide fixing prediction."

According to Zeng, Voltus InsightAI is integrated with the Cadence Innovus Implementation System, which enables customers to significantly reduce the power, integrity, closure, time, and achieve potential PPA gains, effectively reducing today's over-designed power delivery networks (PDNs).

Zeng explains that the main issue is power integrity, which becomes even more challenging on the advanced nodes because designers are packing a lot of transistors in smaller and smaller areas.

"It significantly increases the power density of the design, especially for 5nm and below. In the past, people may have only hundreds of thousands of IR violations in the design and interface, so they can pretty much afford to do it manually," he says. "But for large designs below 5nm, you can easily have hundreds of thousands or millions of violations that you need to address. If you do not have an automatic solution to solve it, then it is impossible for you to close it. This becomes really challenging for the advanced design to close IR drop issues."

Using Voltus InsightAI, customers can use in-design analysis to enhance on-chip and chiplet power integrity. According to Cadence, the technology enables greater engineering efficiency for uncovering issues early and offers key productivity-enhancing features, such as a fast IR inferencing engine, IR drop diagnostics, multi-method fixing, and a fully integrated solution.

First AI-powered EDA Solution in the Market

What makes Voltus InsightAI unique is that it is the first of its kind to use AI technology in the power integrity space for incremental analysis, root cost analysis, and fixing the problem.

"This solution is based on Voltus signoff quality analysis engine, so that whatever you obtain throughout the flow would have a good correlation with your final IR signoff of data," explains Zeng. The platform can also effectively and efficiently reduce IR drop problems with very negligible or no impact at all to the PPA.

Finally, it is the only solution that is tightly integrated into the implementation platform, says Zeng. This makes Cadence the only EDA vendor that has both a leading implementation platform and power integrity solution.

It is no wonder that Voltus InsightAI has received an Innovation R&D Award at EE Awards Asia 2024.Now in its fourth year, EE Awards Asia celebrates the outstanding achievements and honors the innovators in Asia's electronics sector.

"It is really an honor for us to receive this award," says Zeng. "This is the very first award won by Voltus InsightAI, and this is only the beginning. I have a team with the spirit of innovation, and I think you can expect us to continue to deliver more innovative solutions. I hope and I am also confident that this will not be the last time my team wins this award."

This solution is a result of teamwork, according to Zeng. "It was developed from my R&D team and the product engineering team, but we also collaborated with the Innovus R&D and PE teams. We also worked with some cutting-edge customers," he says. "During the development stage there was some skepticism, but the team believed in this direction, and they put their heads down and delivered the solution. I am really proud of their work."

Announced in November 2023, the platform was well-received by the industry. Zeng says they already have seven customers using it for their tapeout project, and more than 35 customers worldwide are actively deploying Voltus InsightAI in their advanced nodes.

What's Next

Zeng says they will continue to innovate and improve Voltus InsightAI. "We had a lot of customer engagements, especially with customers at the leading edge," he explains. "We learned a lot from their designs. Based on their feedback, we can make further enhancements to this algorithm and platform. I think some of the key areas that we can make further enhancements are, first, taking the full chip context into account. A lot of times, when customers are doing the implementation, they are focusing on the block level. But when they do the sign off, they put the entire chip together. Using the full-chip context result to guide the block level fixing, I think, is very important. We have made some really good progress there."

Next, Zeng says his team will continue to focus on improving prevention efficiency and repair methodology in their technology development."

Regarding the integration of AI in EDA platforms, Zeng remains optimistic.

"I think AI will have a transformative impact on the overall EDA industry," he says. He further explains that with AI's ability to learn from existing data, it can help improve the traditional EDA algorithm in areas such as early design exploration, optimization, or sometimes speeding up simulation at a certain stage, and doing verification, placing, or routing.

"I think AI will have a big impact from a productivity point of view, because using an AI assistant that can actually extract the data from a past experience can help guide young engineers or designers to make a better decision about their design or fixing it," says Zeng.

SOURCE EE Times Asia