Flex Logix Co-Founders Awarded Interconnect Patent For Connecting Any Kind Of RAM Between eFPGA Cores To Create Application-Optimized eFPGA Arrays

MOUNTAIN VIEW, Calif., May 15, 2018 /PRNewswire/ -- Flex Logix® Technologies, Inc., the leading supplier of embedded FPGA (eFPGA) IP, architecture and software, announced that an additional switch interconnect patent, U.S. Patent 9,973,194, was issued today to Flex Logix, naming its co-founders Cheng Wang and Geoff Tate as the inventors. This patent, which builds on the tiling interconnect patents issued to Flex Logix in late 2017 and early 2018, highlights a breakthrough technology feature of the company's EFLX® platform, which enables the integration of any kind and amount of RAM between tiles of eFPGA arrays using silicon proven building blocks. This solution, called RAMLinx, enables customization of an eFPGA array to exactly fit customers' needs.

"Traditional FPGA technology used by our competition is not capable of achieving the flexibility and advantages that this patent describes," said Geoff Tate, CEO and co-founder of Flex Logix. "This is a major competitive advantage for our customers because their applications require many different types of RAM in various amounts.  Traditional FPGA technology offers only "block RAM," or dual port RAM, typically in a fixed ratio of RAM to LUTs.  With the Flex Logix architecture, customers can have no RAM, a little RAM or a lot of RAM and they can specify single-port RAM, dual-port RAM, and the type of RAM including specialty RAM such as TCAM."  In addition, the RAM can optionally have parity or ECC as needed.

The technology described in this new patent builds on the tiling architecture of the EFLX eFPGA to utilize the otherwise unused input and output pins of each tile not on the perimeter of the array to provide flexible connections to any kind of RAM located between the tiles of the eFPGA array.  The ArrayLinx mesh connection is routed over top of the RAMs to provide connectivity between tiles of the EFLX eFPGA.  The integrated RAM is an integral part of the eFPGA array and is programmed by the EFLX compiler.  A RAMDEF file informs the EFLX compiler of the characteristics of the integrated RAM.  Typically, the integrated RAM is based on TSMC Memory Compilers, but could also be custom RAM the customer supplies such as TCAM.

The idea of integrating RAM between tiles can also be extended to integrating any kind of custom logic block between tiles – again enabling customization of an eFPGA array to exactly fit the customer's needs.  As with the RAM, the custom logic block, e.g., a digital signal processor, is connected to the logic tiles via the otherwise unused input and output pins of one or more of the adjacent tiles. 

About Flex Logix           
Flex Logix, founded in March 2014, provides solutions for reconfigurable RTL in chip and system designs using embedded FPGA IP cores, architecture and software. The company's technology platform delivers significant customer benefits by dramatically reducing design and manufacturing risks, accelerating technology roadmaps, and bringing greater flexibility to customers' hardware. Flex Logix has secured approximately $13 million of venture backed capital, is headquartered in Mountain View, California and has sales rep offices in China, Europe, Israel, Japan, Taiwan. More information can be obtained at http://www.flex-logix.com or follow on Twitter at @efpga.

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Copyright 2018. All rights reserved. Flex Logix and EFLX are registered trademarks of Flex Logix, Inc.

SOURCE Flex Logix Technologies, Inc.

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