NEW YORK, Jan. 24, 2013 /PRNewswire/ -- Reportlinker.com announces that a new market research report is available in its catalogue:
http://www.reportlinker.com/p01084114/FOWLP--Embedded-Die-Packages.html#utm_source=prnewswire&utm_medium=pr&utm_campaign=Manufacturing
FOWLP TECHNOLOGY IS LOOKING FOR NEW DRIVING FORCES BEYOND INTEL MOBILE'S PUSH
After growing fast since Infineon's strong push for eWLB technology commercialization, the FOWLP market activity reached the $100M market valuation last year. This young industry will need to wait for the 2015 – 2016 time frame to reach $200M market as the demand will shift from IDMs to leading fab-less wireless IC players (such as Qualcomm, Broadcom, Mediatek, etc…) and will be supported by the solid infrastructure of 'top 4' major assembly houses.
Additionally, to bend the rules, we also decided to propose in this report an alternative scenario for FOWLP market evolution. Indeed, regarding the numerous rumors linked to this space, several feedbacks pushed us to propose an optimistic forecast model, making the market starting growing fast as soon as 2013. This enthusiastic scenario would be linked to the following players' activity: Spreadtrum (CN), Maxim (US), ADL (TW), Mediatek (TW).
However, low reliability on large package body size and lack of flexibility in the IC to package co-design process are the two main factors limiting the wide application scope of FOWLP technology on the wireless IC market today. Indeed, FOWLP technology impose a specific re-design of the chip for efficient integration into the package: both Infineon and STEricsson (who already have products on the market) spent almost 18 month to re-design their baseband and RF-Transceiver SOCs in order to place the pads at optimized locations and match with a single RDL, 0.5mm board pitch eWLB package design. It is quite a lot of restrictions for most IC designers of the world to adopt this new package technology efficiently, especially for fabless chip companies. This is why only big semiconductor IDM companies having IC-to-package co-design environment well established in-house can drive and support the initial grow of this new wafer-level-packaging platform at its early beginning.
TWO MAIN OSATs SUPPORTING FOWLP INFRASTRUCTURE TODAY. FOUR MORE PLAYERS TO COME NEXT!
FOWLP is clearly the "Middle-end" platform of choice for packaging assembly & test 'OSAT' suppliers of the IC industry, as all implies a simplification and consolidation of the entire packaging, assembly & test and supply chain inside one single factory.
NANIUM (PT) and STATS ChipPAC (SG) shared more than 80% of the $107M FOWLP activity revenue last year, mainly driven by Intel Mobile's volume demand on eWLB production. While ASE (TW) is shutting down its 200mm eWLB operations this year to focus on future generation FOWLP technologies, many OSAT players are presently in qualification phase such as ADL (TW), Amkor (KR) and NEPES (SG). Additional packaging houses are expected to come onboard in the 2013 – 2014 time frame such as TSMC (TW), SPIL (TW) and J-Devices (JP). More details on the supply chain challenge and the partnership already in place are provided in this research report update.
EMBEDDED DIE PACKAGE PLATFORM SUCCESSFULLY ENTERED THE SiP MODULE BUSINESS
Meanwhile, the embedded die in package industry has taken a giant step forward in 2011 since AT&S (AT) and TI (US) started the commercialization of microSiP DC/DC converter modules with critical mass volume, production of >100M units this year, driven by the mobile market. Rohm (JP) and Epcos-TDK (JP) would be the second source of the same microSiP power conversion module in the mobile handset supply chain of RIM (CA). IC substrate suppliers Taiyo-Yuden (JP) and Fujikura (JP) are also getting ready to ramp-up their internal assembly lines for embedded die packaging. This will bring the total number of players to 4 in the near future, with separate supply chains able to support the embedded die in package technology commercialization.
Today, main roadblocks for embedded die package commercialization are mainly linked to low manufacturing yields (75-85% overall) and supply chain settlement issues in both the embedded die wafer preparation as well as in back-end assembly & test operations. Again, only a large semiconductor IDM company such as Texas Instruments (Us) could successfully lead the commercialization of this new packaging assembly platform by filling the gaps (in terms of investment, risk and know-how) and settle the supply chain.
The most pragmatic approach to commercialize embedded die package technology will be to initially start with simple, low cost, low I/Os, small die analog & power IC applications (such as DC/DC converter modules, IPD networks, RFID, Power MOSFET, IGBT modules, auto-focus driver ICs, etc…)
Embedded die packaging is supported by a game changing, low cost, panel area, PCB based infrastructure that has the potential to create a new space, an alternative supply chain for today's well established package standards such as QFN/SOT/WLCSP/BGA platforms. Being intrinsically "3D" capable, the technology is well positioned to meet the future requirements of miniaturized, low cost 3D SiP module configurations.
Today, first generation's of FOWLP and embedded die package technologies are not really competing as they are driven by different players and will initially target very different application spaces. However, this situation is likely to change radically in the near future as "2nd generation" derivatives of both platforms appear on the market.
KEY FEATURES OF THE REPORT
• Analysis of both FOWLP and Embedded die package technologies
• Key market drivers, benefits and challenges application by application
• Technology roadmaps and manufacturing tool-box related to embedded wafer level packages
- Key equipment: for 200mm / 300mm / Panel manufacturing
- Specific material selection coming from both FE / BE / PCB / LCD areas
• Supply chain perspectives, key players and emerging infrastructure for Embedded WLP
- Analysis of the rationales behind the different possibilities of FOWLP and chip embedding implementations (chip first / chip last, single die / multi-die / SiP / PoP module, etc …)
• Package cost structure analysis based on real products available on the market
COMPANIES CITED IN THIS REPORT
3D-Plus, ADL Engineering, ADTEC Engineering, Amkor, ams, Analog Devices, AT&S, Aptos, Asahi Glass, ASE, ASM, Atotech, Broadcom, Bosch, Camtek, Casio Micronics, CIRETEC, CMK, Compass Technology, CSR, Datacon, Daeduck, Denso, Dialog Semiconductor, Dow Corning, DuPont Electronics, Dyconex, Epic, Epcos TDK, EVGroup, Fico Molding, Flip-chip International, Fraunhofer-IZM, Freescale, Fujitsu, HD Microsystems, HEICO, SK Hynix, Ibiden, Imbera, IME, IMEC, Infineon, Invensas, IPDiA, ITRI, King Dragon International, KYEC, Leti, Lintec, LG Electronic, Micron, MicroChem, Mitsui, Murata, Nagase ChemteX, NANIUM, NEC Electronics, Nitto Denko, Nokia, NSC, NXP, OptoPac Oki Electric, ORC, Panasonic, Qualcomm, Renesas, Rohm & Hass, Rudolph technologies, Samsung, SEMCO, Shinko Electric, SPIL, STATS ChipPAC, ST-Ericsson, STMicroelectronics, SPTS, SMIC, Shin-Etsu, SÜSS Microtec, Taiyo Yuden, TDK, Tessera, Texas Instruments, tok, Tong Hsing, Toray chemical, Toray Engineering, Toshiba, Towa, Triquint, UMTC, Unimicron, Unovis, UTAC, Vertical Circuits, Wolfson Microelectronics, Yamada and more…
Scope of the Report & Definitions p 4
Executive Summary p 11
Embedded Die in Substrates of Active ICs & Passive Components p 48
• Motivations and Drivers p 49
• Application focus for Embedded die package commercialization p 64
- cell-phone & consumer, automotive, medical applications
• 2010-2020 market forecasts for Embedded packages p 91
- in package shipments (M units)
- in packaging revenues ($M)
• Supply chain emerging for embedded dies p 98
- Players and position in the electronic value chain
- Who is the most aggressive in commercialization?
- Who is doing what: partnerships identified
• Equipment & Material Toolbox for Embedded die p 129
- Technology flavors for embedded package. Chip first versus chip last?
- Single die embedding versus SiP module? Challenges related to yield & supply chain
• Cost structure for Embedded package manufacturing p 134
• Conclusion on "sweets spots" for the introduction of Embedded die technology in the short / medium / long term p 138
FOWLP Technology Development p 140
• Motivations and market drivers p 144
- Form factor, Cost, electrical and thermal performance
• Supply chain emerging for FOWLP p 162
- Players and position in the electronic value chain. Who is the most aggressive in commercialization? Who is doing what: partnerships identified
• 2010-2020 market forecasts for FOWLP type of packages p 174
- In Package shipments (M units)
- In epoxy wafer production (wspy eq.)
- In Packaging revenues ($M)
• FOWLP technologies & challenges p 202
- 1st generation versus 2nd generation FOWLP. "Passive integration with FOWLP technologies
• Equipment & Materials for FOWLP p 213
- Challenges in new material selection and missing equipment
- Technology roadmap for FOWLP development
• 2.5D integration trends based on FOWLP and silicon / glass interposer mix p 227
• FOWLP patent activity summary p 233
• Cost structure for FOWLP p 265
• Evolution to Panel-scale-packaging p 252
Conclusion & Perspectives p 281
Appendix p 287
• Yole Développement company presentation & services
To order this report:
Manufacturing Industry: FOWLP & Embedded Die Packages
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Nicolas Bombourg
Reportlinker
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