SAN MATEO, Calif., Oct. 24, 2019 /PRNewswire/ -- SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, announced today a portfolio of new, high-performance IP for scalable SoC Designs. Introduced at the Linley Fall Processor Conference, the industry's premier processor event, SiFive Chief Architect Krste Asanovic detailed the new SiFive U8-Series Core IP, and the SiFive optimized HMB2E+ solution.
New SiFive U8-Series Core IP
The new SiFive U8-Series Core IP is based on the RISC-V ISA and is a superscalar design, featuring a scalable out-of-order pipeline with configurable options for use in real-time or application processors. Designed to offer class-leading energy- and area-efficiency, the SiFive U8-Series microarchitecture offers excellent performance, with the customizability customers have come to require from SiFive.
The SiFive U8-Series microarchitecture was designed to offer over 1.5X improvement in area efficiency and performance-per-watt vs. the competitor product available today. The SiFive U8-Series Core IP is multi-core capable with Linux capable memory management unit to enable general application processor designs. The SiFive U8-Series microarchitecture can support real-time mode for mission-critical operation, leverage features typically seen before only on high-end designs implemented in advanced process nodes.
Featuring optional floating-point unit, customized instruction extension capability, and RISC-V vector extension support, the SiFive U8-Series Core IP can be configured and customized perfectly to the target use case, whether in Automotive or AI at the Edge or End-point application.
New SiFive IP for Deep Learning
The new SiFive HBM2E+ IP is designed to enable the latest compute-intensive workloads, including deep learning processing in high performance compute, data center, and edge AI devices. Featuring industry-standard interfaces, SiFive HBM2E+ IP is simple to integrate into new designs and enables an optimized CPU to memory path, using a scalable interface to enable chiplet designs as well as performance.
Validated in a leading-edge 7nm process technology, the SiFive HMB2E+ solution offers memory bandwidth up to 400Gbps, or 3.2Gbps per pin. HBM's stacking properties enable smaller footprints and lower power consumption than similar capacity DDR-style memory, with higher bandwidth, critical for processing memory-intensive deep learning workloads.
Customizability Without Fragmentation
Key growth markets are demanding more efficient, faster processing of data locally, as the need for AI at the edge and end-point rapidly increases. New domain-specific designs for data-center accelerators, automotive systems, industrial IoT, and consumer IoT devices, are quickly emerging as the favored design paradigm, perfectly aligned to SiFive's methodology, portfolio, and expertise.
The adoption of both RISC-V ISA based configurable cores and open-source interconnects to enable high-performance silicon ensures customized designs are not fragmented. SiFive custom instruction extensions deliver specific accelerations tailored to the workload without impacting base ISA or other formal extension compatibility and are supported by industry-standard tools such as IAR Workbench.
SiFive's new processor core and memory interfaces combine the necessary IP for success in the high-growth markets that require domain-specific application processors. Automotive, IoT Edge and End Point AI applications, and Data Center Accelerators designs can all benefit from the scalable performance and processing power delivered by SiFive Core IP and HBM2E+.
"It's exciting to see SiFive's release of the U8-Series out-of-order microarchitecture," said Kevin Krewell, principal analyst at TIRIAS Research. "New, higher performance Linux-capable cores enable SiFive to enter new markets and broaden RISC-V applications. Combining both open-source standard ISAs and interconnects, along with common industry-standards and new high-bandwidth memory technology, enables customization and to address a wider set of application markets and increasing the company's TAM."
"The introduction of the new, SiFive U8-Series microarchitecture is a major milestone," said Naveed Sherwani, CEO, SiFive. "The availability of a scalable out-of-order RISC-V processor to use in domain-specific applications heralds a new era of configurable, customized SoC designs based on RISC-V. SiFive is continuing to lead with IP and silicon solutions for automotive, data center attach, and Edge AI."
SiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, www.sifive.com.