SAN MATEO, Calif., May 1, 2019 /PRNewswire/ -- SiFive, the leading provider of commercial RISC-V processor IP and custom SoC solutions, today announced it is expanding into the metropolitan Portland area with the opening of a development office in Beaverton, Oregon. The primary mission of the office is to provide local support to existing SiFive customers and partners as well as to help fuel the mass adoption of the RISC-V Instruction Set Architecture (ISA) that is taking place in the region and throughout the world. The office will be managed by Sunil Shenoy, senior vice president and general manager of the RISC-V Business Unit at SiFive, and Ahmet Houssein, vice president of business development for HPC and data center solutions at SiFive. SiFive's current development tools team, established in September 2018 and headed by Rick Leatherman, a local technology entrepreneur and now director of development tools for SiFive, will also operate from the new Beaverton office space.
"The Portland area has become an international center of open source hardware development," Shenoy said. "There is a steady stream of RISC-V based innovation at both large and small companies in the area. Establishing a presence in the robust Silicon Forest underscores our commitment to fostering the momentum of the RISC-V revolution."
Houssein added: "Having a team in Beaverton will help us better address the needs of data center designers and partners who are utilizing RISC-V based processors to achieve optimal performance. We look forward to accelerating their RISC-V based product development efforts and enabling many new and innovative use cases."
The opening of the SiFive office in Beaverton coincides with the FOSSi Foundation's premier North American open source digital design conference, Latch-Up. SiFive is proudly sponsoring this event to further the advancement of the RISC-V ISA. SiFive co-founder and chief engineer, Andrew Waterman, an ardent supporter of open source hardware development, will attend. Jack Koenig, software engineer at SiFive and a maintainer of the Chisel (Constructing Hardware in a Scala Embedded Language) and FIRRTL (Flexible Intermediate Representation for RTL) projects, will present "Higher-Order Hardware Design with Chisel3." Additionally, Aliaksei Chapyzhenka, software engineer at SiFive, will present "Diagrams and System Visualization in Chip Design." SiFive will also demonstrate its Linux-capable HiFive Unleashed RISC-V reference platform. The conference will take place in Portland, May 4-5, 2019. For more information, or to register to attend, please visit https://fossi-foundation.org/latchup/.
SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit www.sifive.com.
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