SAN MATEO, Calif., June 25, 2018 /PRNewswire/ -- SiFive, the leading provider of commercial RISC-V processor IP, today announced the availability of its E2 Core IP Series, configurable low-area, low-power microcontroller (MCU) cores designed for use in embedded devices. The E2 Series extends SiFive's product line with two new standard cores, the E21, which provides mainstream performance for MCUs, sensor fusion, minion cores and smart IoT markets; and the E20, the most power-efficient SiFive standard core designed for microcontrollers, IoT, analog mixed signal and finite state machine applications. Additionally, the company announced enhancements to its existing standard E3 and E5 Core IP Series.
The SiFive E20 and E21 are designed for markets that require extremely low-cost, low-power computing, but can benefit from being fully integrated within the RISC-V software ecosystem. Fully compatible with the exact same software stack, tools, compilers and ecosystem vendors as other higher performance SiFive cores, the E2 Series enables these new markets to take advantage of the robust software ecosystem that has been exponentially growing since SiFive first introduced commercial RISC-V cores in 2016. Both cores are fully synthesizable and verified soft IP implementations that scale across multiple design nodes. The new product series provides a variety of new features, including a fully configurable memory map, multiple configurable ports, tightly integrated memory (TIM), fast IO access and a new CLIC interrupt controller for extremely fast interrupt response, hardware prioritization and pre-emption.
Furthermore, SiFive gives designers the ability to configure a SiFive RISC-V Core Series to their specific application needs, with the ability to fine-tune performance, microarchitectural features, area density, memory subsystems and more within a given Core Series. Customers can either directly leverage the silicon-proven standard SiFive Core IP like the E21, or use it as a starting point for their own customizations.
"SiFive's Core IP is the foundation of the most widely deployed RISC-V cores in the world, and represent the lowest risk and fastest path to customized RISC-V based SoCs," said Yunsup Lee, co-founder and CTO, SiFive. "Our Core IP Series takes advantage of the inherent scalability of RISC-V to provide a full set of customizable cores for any application - from tiny microcontrollers based on our new E2 Core IP Series to our previously announced, Linux-capable, multicore U Core IP Series."
In addition to announcing the new E2 Core Series, SiFive also expanded its E3 and E5 Series to support coherent multicore configurations for high-performance embedded applications. In addition to multicore support, the E3 and E5 Series have a new enhanced multiplication unit which allows the E31 and E51 Standard Cores to achieve over 3 CoreMarks/MHz while still using open-source GCC compilers. The E3 and E5 Series are ideal for high-performance, real-time applications such as storage, industrial, modems and networking.
SiFive will demonstrate the E21 at the Design Automation Conference at San Francisco's Moscone Convention Center through June 27 in the RISC-V Foundation booth, No. 2638. For more information on SiFive's RISC-V Core IP including full datasheets, specifications and app notes, visit www.sifive.com/core-ip/.
About SiFive SiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Huami, SK Telecom, Western Digital and Intel Capital. For more information, visit www.sifive.com.