SAN JOSE, Calif., April 20, 2020 /PRNewswire/ -- Silexica (silexica.com) has announced the release of SLX FPGA 2020.1, which can now process and analyze the hls::stream template class and support array partitioning of ap_int and ap_fixed data types from Xilinx. These enhancements extend SLX FPGA's ability to analyze C/C++ code further, make better decisions, and further accelerate performance.
An example of the performance improvements is demonstrated in Silexica's latest white paper, SLX FPGA Beamformer. It shows how SLX FPGA optimizes an algorithm used for beamforming in radar applications and achieves more speed-up compared to an expert-level, hand-optimized HLS implementation in less time.
"SLX FPGA takes the guesswork out of high-level synthesis design," said Philippe Manet, CEO of ECSPEC. "Since adding SLX FPGA to our design methodology, we've significantly reduced our development time. In one of our designs, a complex image processing algorithm, we were able to achieve better performance with SLX in one week compared to hand-coded RTL, which took two months."
New Features Include:
- Processing and analysis of hls::stream template class
- Support for array partitioning of ap_int and ap_fixed data types from Xilinx
- Improved reduction pattern identification on arrays allows more data-level parallelism loops to be identified in code
- Added support for Xilinx Vivado HLS 2019.2 as well as Ultrascale, Ultrascale+ families, and RFSoC devices.
Ease-of-Use Enhancements Include:
- A new function mapping editor serves as a central entry point into the analysis and optimization flow, giving an overview of application structure, top-level hardware functions, loops, and synthesizability issues.
- Within the function mapping editor, a new filter view enhancement allows users to sort, expand, filter, and collapse how loops and design hints are displayed.
"The demands of the industries continue to drive our partners and customers in the Fintech, Automotive, and Aerospace and Defense markets to reduce development time and increase design performance to meet their goals," said Jordon Inkeles, VP of Product at Silexica. "SLX FPGA 2020.1 directly addresses and tackles their demand for assistance in optimizing algorithms for HLS."
Please contact us if you are interested in seeing a live demo or exploring an evaluation of SLX FPGA.
About SLX FPGA
SLX FPGA accelerates the performance optimization of C/C++ code for high-level synthesis (HLS) in Xilinx's Vivado™ and Vitis™ HLS design flows. SLX FPGA also enables faster-time-to-market by leveraging the benefits of HLS for FPGA design entry. These benefits include improved productivity through designing at a higher level of abstraction, faster simulation vs. RTL simulation, and higher QoR through high-level optimizations and design space exploration. SLX FPGA expands and disrupts the use of HLS, democratizing the usage of FPGAs for software developers.
SLX FPGA saves months of development effort by performing:
- Guided and automatic refactoring of non-synthesizable code written in C/C++
- Detection of C/C++ code that can be executed in parallel to optimize performance
- Automatic insertion of optimized pragmas to guide the Vivado HLS and Vitis compiler
Silexica provides software development tools allowing technology companies to take innovative IP and intelligent products from concept to deployment rapidly. Enabled by metric-driven software analysis and execution behavior insights, the SLX programming platform disrupts the journey from software to application-specific hardware.
Founded in 2014, Silexica is headquartered in Germany with offices in the U.S., Japan and Pakistan. It serves innovative companies in the automotive, robotics, wireless communications, aerospace and financial industries and has received $28M in funding from international investors.
SLX FPGA 2020.1 Extends C++ Support and Advanced Array Partitioning
Silexica (silexica.com) has announced the release of SLX FPGA 2020.1 which can now process and analyze the hls::stream template class and support array partitioning of ap_int and ap_fixed data types from Xilinx
SOURCE Silexica GmbH