MOUNTAIN VIEW, Calif., May 10, 2017 /PRNewswire/ --
- Intelligent replay of RTL simulation data on a gate-level netlist for power analysis accurate within 5% of signoff
- Targeted analysis of specific areas of the design during key power consumption windows mitigates exhaustive gate-level simulations and significantly accelerates power analysis flows
- Enables SoC designers to make timely design optimizations to achieve power targets and on-time product delivery
Synopsys, Inc. (NASDAQ: SNPS) today announced the availability of its PowerReplay solution to enable early and fast gate-level power analysis with accuracy within 5% of power signoff. Energy efficiency has become a key criterion in complex designs that increasingly need to achieve stricter power targets. The new PowerReplay solution, in combination with Synopsys PrimeTime® PX gate-level power analysis, enables SoC teams to achieve accurate power results much earlier and perform design optimizations before the final power signoff.
"Realtek's highly integrated SoCs deliver maximum power efficiency for multimedia and consumer electronics solutions," said Yee-Wei Huang, vice president and spokesman at Realtek. "Given the tight deadlines to achieve the power targets demanded of next-generation designs, our SoC teams need to analyze gate-level power consumption from the get-go. The Synopsys PowerReplay solution delivers highly accurate power analysis earlier and faster, enabling us to implement design optimizations within schedule."
SoC design teams utilize sophisticated low-power techniques to reduce power consumption. However, thorough power analysis often happens much too late in the design flow to allow for changes if the design does not meet power targets. PowerReplay's proprietary technology leverages readily available RTL simulation data to drive the gate-level netlist through an auto-generated gate-level environment, both at the block-level and at the full-chip level. Concurrent runs in conjunction with the targeted application of stimulus on specific areas of the design during key power consumption windows significantly reduce turnaround time. This enables earlier and faster generation of gate-level switching data for PrimeTime PX power analysis without waiting for gate-level environment bring up and exhaustive gate-level simulations. PowerReplay enables SoC teams to make design optimizations much earlier, resulting in more predictable on-time delivery of products within power specifications.
"We continue to collaborate with our customers on the verification and analysis of the industry's most power-efficient SoCs," said Ajay Singh, vice president of engineering in Verification Group at Synopsys. "The new PowerReplay solution, in combination with Synopsys PrimeTime PX – the golden, trusted signoff solution for power analysis – addresses designers' need for signoff-level power analysis earlier in the design flow and enables them to achieve their demanding power targets."
Availability & Resources
Power Replay is now in General Availability.
Learn more about PowerReplay: www.synopsys.com/PowerReplay
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
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SOURCE Synopsys, Inc.