Technology Analysis of 2-Axis OIS Gyroscopes - Research and Markets
DUBLIN, Feb 14, 2017 /PRNewswire/ --
Research and Markets has announced the addition of the "2-Axis OIS Gyroscopes: Technology Analysis" report to their offering.
This market is only made with high-end smartphones and mainly two players shared the pie: InvenSense with 49% and STMicroelectronics with 39% of the market.
The 2-axis gyroscopes are located inside the camera module of high-end smartphones and the main constraint consists on providing a small footprint and more importantly a small thickness.
The thickness was the same than standard LGA or QFN packages some years ago, close to 1mm. Now the standard is 0.65mm, and both InvenSense and STMicroelectronics released a device with this thickness.
InvenSense has been the first, with the IDG-2030, a 2.3x2.3x0.65mm gyroscope which is still the smallest on the market. Since its introduction we found it in several smartphones from various OEM. The IDG-2030 uses the same Nasiri platform as other InvenSense inertial devices, making the wafer-level integration of the MEMS sensor on top of the ASIC, thus providing only one die in the final LGA package.
STMicroelectronics on its side released the L2G2IS some month after the IDG-2030 and shares the same dimensions. The device is manufactured using the same THELMA process than all STMicroelectronics inertial devices. This THELMA platform requires a two dies approach which became to be very challenging for very thin package integration. At the end both players have been able to propose very low cost gyros due to die size reduction and process optimization.
Key Topics Covered:
Overview/Introduction
Company Profile & Supply Chain
Physical Analysis
- Package
- Package views and dimensions
- Package opening
- Package cross-section
- ASIC Die
- View, dimensions, and marking
- Delayering and process
- Cross-section
- MEMS Die
- View, dimensions, and marking
- Cap Removed
- Sensing Area
- Cross-sections (Sensor, Cap, Sealing)
Manufacturing Process Flow
- ASIC front-end process
- ASIC wafer fabrication unit
- MEMS process flow
- MEMS wafer fabrication unit
- Packaging process flow
- Package assembly unit
Cost Analysis
- Yields hypotheses
- ASIC front-end cost
- ASIC back-end 0: probe test and dicing
- ASIC wafer and die cost
- MEMS front-end cost
- MEMS back-end 0: probe test and dicing
- MEMS front-end cost per process steps
- MEMS wafer and die cost
- Back-end: packaging cost
- Back-end: packaging cost per process steps
- Back-end: final test cost
- Gyroscope component cost
Estimated Price Analysis
For more information about this report visit http://www.researchandmarkets.com/research/dg5gzg/2axis_ois
Media Contact:
Research and Markets
Laura Wood, Senior Manager
For E.S.T Office Hours Call +1-917-300-0470
For U.S./CAN Toll Free Call +1-800-526-8630
For GMT Office Hours Call +353-1-416-8900
U.S. Fax: 646-607-1907
Fax (outside U.S.): +353-1-481-1716
SOURCE Research and Markets
Share this article