TSMC Certifies Cadence Innovus Implementation System on 10nm FinFET Process

SAN JOSE, Calif., Sept. 16, 2015 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its Cadence® Innovus™ Implementation System has achieved V0.9 certification for TSMC's 10nm FinFET process and is currently on track to complete V1.0 in Q4 2015. The Innovus Implementation System is a next-generation physical implementation tool that incorporates integrated signoff engines that have been validated by TSMC on high-performance reference designs, providing customers with a fast path to implementation, closure, and optimal power, performance and area (PPA).

The Innovus Implementation System offers customers key technologies needed to stay in front of the competition using the TSMC 10nm process. Some of the technology capabilities include:

• GigaPlace™ solver-based placement technology – The pin-access-aware feature ensures the cells are placed in accordance with 10nm orientation, coloring and edge-constraint requirements to avoid downstream routing issues, while enabling designers to meet aggressive timing and area metrics
• Embedded accurate extraction, delay calculation and power calculation engines – Integration with signoff tools—Quantus™ QRC Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution and Physical Verification System—ensures that there are consistent results across the different steps of the 10nm implementation flow, which improves design closure and signoff schedule predictability
• Global optimization engines – Provides optimal performance and power during implementation while taking 10nm process variation into account
• Massively parallel architecture – Increases capacity and drives better turnaround times without compromising the quality of results (QoR), despite the tight constraints imposed by 10nm technology geometries

For more information on the Innovus Implementation System, please visit www.cadence.com/news/innovus.

"The Innovus Implementation System allows customers to achieve TSMC's 10nm FinFET process benefits of smaller area, higher performance and lower power consumption with a reduced turnaround time," said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. "Our continued collaboration with TSMC on the Innovus Implementation System certification provides customers with confidence that they can attain consistent results and meet aggressive schedules."

"We worked closely with Cadence to certify the Innovus Implementation System to meet TSMC's 10nm FinFET requirements," said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. "Through the certification collaboration, we provide design solutions for our joint customers to deliver innovative, advanced-node designs to market."

In related news, please see the Cadence press release titled, "Cadence Digital, Custom/Analog and Signoff Tools Achieve TSMC Certification for 10nm FinFET Process," at http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=091615_tsmc10nmFFcert.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.

This news release contains certain forward-looking statements, including expectations for the timing and results of certification efforts and collaboration with TSMC, that are based on our current expectations and involve numerous risks and uncertainties that may cause these forward-looking statements to be inaccurate. This news release also contains forward-looking statements attributed to third parties, which reflect their expectations as of the date of issuance. Risks that may cause these forward-looking statements to be inaccurate include among others: Cadence's technology and products described in this press release may not perform as expected, Cadence's certification and collaboration efforts may be altered or delayed, or the other risks detailed from time-to-time in our Securities and Exchange Commission filings and reports, including, but not limited to, our most recent quarterly report on Form 10-Q and our annual report on Form 10-K. We do not intend to update the information contained in this press release.

© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks and GigaPlace, Innovus, Quantus, Tempus and Voltus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
408-944-7039
[email protected]

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SOURCE Cadence Design Systems, Inc.

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