New product capabilities deliver leading performance, capacity, and industry-first hardware-assisted test-automation capabilities to accelerate AI silicon innovation from data center to edge
Key Highlights
SUNNYVALE, Calif., March 11, 2026 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced advancements across its leading hardware-assisted verification (HAV) portfolio, including new hardware platforms and capabilities to support the ever-expanding demand for AI chip verification from the data center to the edge. Synopsys HAV platforms, powered by the company's unique software-defined capabilities, set new performance, scalability, and use case benchmarks for verifying the world's most sophisticated multi-die and AI chips amidst compounding design complexity and time-to-market requirements.
AI chip verification complexity is escalating rapidly as large language models continue to double in size roughly every four months, and interface data rates advance at a 2x rate every three years. Simultaneously, edge AI architectures are driving aggressive throughput, latency, and power‑efficiency targets that further expand the design and validation workload. To keep pace, the industry requires HAV solutions to support broader application coverage and run quadrillions of verification cycles, enabling first‑time‑right silicon and a seamless ability to integrate heterogeneous AI systems.
"As AI-driven systems become more complex, verification must scale just as quickly. Hardware-assisted verification is no longer optional. It is critical to meeting aggressive time-to-market goals and ensuring silicon readiness," said Salil Raje, Senior Vice President and General Manager, Adaptive and Embedded Computing Group, AMD. "FPGA-based emulation and prototyping play a central role in that effort by accelerating system bring-up and enabling earlier software development. Our collaboration with Synopsys reflects that focus. Through joint optimization of Synopsys ZeBu with the AMD Vivado™ software stack, and by leveraging AMD EPYC™ processors for compute acceleration, we are reducing compile times and helping customers move to accurate system models faster."
"As AI becomes more pervasive across almost every industry and products are now workload-optimized and silicon-powered, building high confidence early that the workloads are running to spec on the silicon under development is critical," said Ravi Subramanian, Chief Product Management Officer at Synopsys. "Our software-defined, hardware-assisted verification solutions deliver continuous innovation. They are a powerful force multiplier to scale verification productivity and meet the growing demand for pre-silicon development across industries."
The latest advancements across Synopsys' software-defined hardware-assisted verification portfolio, include:
Breakthrough performance and capacity for the AI era: The latest software-defined updates and modular HAV are available across the ZeBu and HAPS platforms. Of note, with these updates, the industry's highest capacity-scalable emulation platform, ZeBu Server 5, supports complex designs to meet the demands of mega designs supporting data center AI training and inference, GPU, custom accelerators, and networking IPU/DPU workloads. Modular HAV for HAPS enables the largest prototypes for software development, with further improvements for compute, storage, and bring-up capabilities.
New HAPS and ZeBu platforms: The new HAPS-200 12 FPGA and ZeBu-200 12 FPGA systems address the complexity and high-performance requirements for data center-sub-system, mobile, client, server, consumer, and edge AI applications. They deliver 2x higher capacity compared to previous 6 FPGA platforms utilizing the flagship AMD Versal™ Premium VP1902 adaptive SoCs, offering EP-Ready Hardware-enabled configurability between prototyping and emulation. Synopsys also introduces the new HAPS-200 1 FPGA platform as a desktop system ideal for IP verification and software bring-up using Synopsys Interface Prototyping Kits.
"As NVIDIA's AI platforms have become software‑defined to meet rising performance and scalability demands, verification must evolve in the same way," said Narendra Konda, Vice President, Hardware Engineering at NVIDIA. "Synopsys' software‑defined hardware‑assisted verification and the new HAPS‑200 12 FPGA systems are accelerating our system‑level verification and validation, helping us deliver complex AI platforms on aggressive schedules. And, Synopsys modular hardware-assisted verification enables deeper collaboration across our ecosystem."
Software-defined HAV capabilities extend system lifetime value: Continuous software improvements deliver compounding performance gains, increased debug productivity, as well as additional use case capabilities for both new and installed systems. The Synopsys HAV portfolio supports new, industry-first Hardware-Assisted Test Solutions, test automation capabilities that allow teams to stress corner cases for processor, memory, and I/O subsystems as well as full-system coherency validation and observe system behavior under realistic workloads in emulation long before silicon is ready. For mixed-signal and system-level designs, Real-Number Models (RNM) emulation enables fast, scalable abstraction of analog behavior within digital-centric verification flows for faster software bring-up. For safety-critical and high-reliability designs, new fault emulation capabilities enable scalable fault injection and analysis across RTL simulation, emulation, and prototyping.
"Verifying hardware for our highly anticipated rack-scale AMD Helios solution – marked by massive AI scale, complex subsystems, and robust software stacks – demands scalable and versatile verification platforms," said Alex Starr, Corporate Fellow, AMD. "The Synopsys software-defined, HAV capabilities with EP-Ready Hardware are critical to how we perform CPU, GPU, and AI subsystems verification as well as full-system validation. Teams can also cover an expanded number of use cases in the pre-silicon phase, encompassing analog, digital, and software design verification using Real-Number Models (RNM) in emulation. As well, the flexibility to reconfigure and reuse hardware across projects and move seamlessly between emulation and prototyping as AI designs grow in both physical size and software stack volume are essential to delivering the high-performance, interoperable AI infrastructure at scale needed to meet the world's growing AI demands."
Availability & Additional Resources
Software-defined enhancements are being rolled out continuously across the HAV portfolio, with the new capabilities available to users today. The new EP‑Ready HAPS-200 12 FPGA and ZeBu-200 12 FPGA platforms are available today and in Q3 2026, respectively. HAPS-200 1 FPGA platform is available today.
Follow Synopsys Converge 2026 News and Updates
Synopsys Converge is taking place March 11-12, 2026, at the Santa Clara Convention Center. Follow news and updates as well as keynote details and replays via the Synopsys Converge Newsroom, on LinkedIn, and on X.
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Learn more at www.synopsys.com.
© 2026 Synopsys, Inc. All rights reserved. Synopsys, Ansys, the Synopsys and Ansys logos, and other Synopsys trademarks are available at https://www.synopsys.com/company/legal/trademarks-brands.html. AMD EPYC, Versal, Vivado and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other company or product names may be trademarks of their respective owners.
Contacts
Media
Kelli Wheeler: [email protected]
Pete Smith: [email protected]
[email protected]
SOURCE Synopsys, Inc.
Share this article