Open Compute Project Foundation and JEDEC Drive Open Silicon Innovation
New Chiplet Design Kits Enable New Silicon Supply Chains
AUSTIN, Texas, Feb. 27, 2025 /PRNewswire/ -- Today, the Open Compute Project Foundation (OCP), the nonprofit organization bringing hyperscale innovations to all, and JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, announce the availability of new Chiplet Design Kits for use with today's EDA tools covering Assembly, Substrate, Material and Test developed in collaboration within the OCP Open Chiplet Economy Project. Leveraging the alliance between OCP and JEDEC, these design kits are now part of the Global World Wide Standard JEDEC JEP30: Part Model Guidelines.
The release of the Assembly, Substrate, Material, and Test Design Kits build on earlier joint efforts between the OCP and JEDEC integrating OCP Chiplet Data Extensible Markup Language (CDXML) specification into JEDEC JEP30: Part Model Guidelines, enabling Chiplet builders to provide electronically a standardized Chiplet part description to their customers, paving the way for automating System-in-Package (SiP) design and build using Chiplets.
"The new design kits, developed through collaboration between OCP and JEDEC, promote innovation in SiP design by fostering collaboration and openness, ensuring broad accessibility, and supporting rapid adoption across the semiconductor industry. These kits promote openness, streamline design workflows, and reduce manual interventions, thereby significantly improving design efficiency, scalability, and innovation," said James Wong, Palo Alto Electron, David Ratchkov, Thrace Systems and Michael Durkan, Chair of the JEDEC JEP30 Task Group. The integration of the design kits with the rest of the PartModel enforces consistent terminology across the Chiplets and the rules that support the development of SiP, eliminating the need for re-mapping within the design tools.
- The Assembly and Substrate Design Kits enables efficient integration of heterogeneous Chiplets by defining standardized rule formats and tolerances for key design elements such as geometries, layers, interconnects and assembly processes.
- The Material Design Kit provides a comprehensive framework for defining, evaluating, and validating the material properties and design parameters required for SiP. It focuses on critical elements such as substrates, interposers, redistribution layers and 3D integration technologies. The kit emphasizes the importance of material properties, such as dielectric constants, thermal conductivity and mechanical strength, to optimize performance, reliability and cost-efficiency.
- The Test Design Kit, which is being standardized within JEDEC, enables the planning, design and manufacturing of SiP, with a particular emphasis on testability, enabling standardization of the testing process for Chiplet integration, with a focus on standard definitions for test elements, test flow requirements and definition of test-only elements, and support for test in advanced manufacturing.
"Chiplets have rapidly become the efficient and cost-effective way to develop chips at leading-edge nodes, and have been used successfully to improve SiP performance with cost efficiencies at scale, because the entire chip development cycle is managed in-house at large companies. To provide an open environment where designers drop known-good third-party sourced Chiplets into their designs requires the development of an open marketplace. Recently the OCP took the next step in establishing an Open Chiplet Economy with the opening of the OCP Chiplet Marketplace. Moving forward the OCP intends to become the front door to an open Chiplet marketplace, making available a catalogue of standalone Chiplets, new standardizations, tools and best practices that would be required for a truly open economy," said Cliff Grossner, Ph.D., Chief Innovation Officer at the Open Compute Project Foundation.
The schemas included in the Assembly, Materials and Test design kits as integrated into the JEDEC JEP:30 Part Model Guidelines have been designed to scale to a very large number of Chiplet interconnection points while keeping the schema size manageable. Security is also of utmost importance and all schema files are digitally signed to ensure no corruption, when shared between chiplet buyer to seller.
"There are still many opportunities to create additional standardization efforts bringing together JEDEC's strength in setting global standards for the microelectronics industry with OCP's expertise in specifying system level devices seeding emerging technologies and markets. JEDEC is delighted with this next step in the collaboration with OCP moving the market forward," said John Kelly, President, JEDEC.
"The next inflection point for the silicon supply chain is open, with innovation driven by a collaborative community, just as we have seen with the computing platforms of the cloud computing era. Developing an open stand-alone Chiplet silicon supply chain will require a rethink of this supply chain. Many design decisions made by Chiplet designers will impact packaging, test and verification, and the software stack, which will all be done by separate organizations, unlike today, where most silicon design is done in-house using proprietary processes," said Tom Hackenberg, Principal Analyst in Computing & Software at Yole Group.
About the Open Compute Project Foundation
The Open Compute Project (OCP) is a global collaborative Community of hyperscale data center operators, telecom, colocation providers and enterprise IT users, working with the product and solution vendor ecosystem to develop open innovations deployable from the cloud to the edge. The OCP Foundation is responsible for fostering and serving the OCP Community to meet the market and shape the future, taking hyperscale-led innovations to everyone. Meeting the market is accomplished through addressing challenging market obstacles with open specifications, designs and emerging market programs that showcase OCP-recognized IT equipment and data center facility best practices. Shaping the future includes investing in strategic initiatives and programs that prepare the IT ecosystem for major technology changes, such as AI & ML, optics, advanced cooling techniques, composable memory and silicon. OCP Community-developed open innovations strive to benefit all, optimized through the lens of impact, efficiency, scale and sustainability. Learn more at www.opencompute.org.
About JEDEC
JEDEC is the global leader in the development of standards for the microelectronics industry. Thousands of volunteers representing over 350 member companies work together in more than 100 JEDEC committees and task groups to meet the needs of every segment of the industry, manufacturers and consumers alike. The publications and standards generated by JEDEC committees are accepted throughout the world. All JEDEC standards are available for download from the JEDEC website. For more information, visit www.jedec.org.
Media Contacts
Dirk Van Slyke
Open Compute Project Foundation
[email protected]
Mobile: +1 303-999-7398
(Central Time Zone/CST/Austin, TX)
Emily Desjardins
JEDEC
703-907-7560
[email protected]
(Eastern Time Zone/EST/Arlington, VA)
SOURCE Open Compute Project Foundation
Share this article