SANTA CLARA, Calif., May 10, 2017 /PRNewswire/ -- Algo-Logic Systems announces the release of their third generation Field Programmable Gate Array (FPGA) accelerated CME Group (CME, CBOT, COMEX, and NYMEX) Tick-To-Trade (T2T) System. The sub-microsecond trading solution is ideal for latency sensitive trading firms that need deterministic response times to market opportunities. The CME T2T System is built using Algo-Logic's internally developed, pre-built FPGA IP cores that significantly reduce time-to-market. Unlike other FPGA accelerated trading systems, Algo-Logic's T2T System supports multiple pre-built and customizable triggers as well as the ability to modify fields of an order in logic.
The breakthrough system can be used by traders and market makers to instantly react to changing market conditions by updating or canceling quotes based on latency sensitive market data. The system can also be used to quickly modify legs of a spread and supplement existing complex trade strategies in software with logic in FPGA hardware.
Deep sub-microsecond wire-to-wire latency is achieved by performing all trade operations in FPGA logic. Operations offloaded to the FPGA include processing CME MDP 3.0 tick data on a 10 Gigabit/second (10G) Ethernet link by the integrated feed handler, building the CME Futures & Options (F&O) Order Book from incremental tick data, detecting trading opportunities, and placing trades in the form of FIX orders over the 10G TCP Endpoint. The system is implemented on a standard FPGA card that fits into a 1U rackmount server.
The CME T2T System is seamlessly managed through a software Application Programming Interface (API). A low latency messaging protocol allows traders and market makers to specify trigger conditions and preload orders into the FPGA from software. Algo-Logic's system can be integrated with the client's existing Order Management System (OMS) or interface with a pre-built OMS from Rival Systems. Device parameters, system status, log messages, and event notifications can be easily monitored from a Graphical User Interface (GUI). RESTful APIs are also provided for control and monitoring of the FPGA accelerator.
Components of Algo-Logic's CME T2T System include:
Pre-Built IP Cores in FPGA Logic:
- Ultra Low Latency PHY+MAC: Lowest round trip latency of 89.6 nanoseconds
- CME Feed Handler: Processes MDP3.0 market data with A/B faster feed arbitration
- CME Futures & Options Order Book: Provides L2 snapshots containing Best Bid Offer (BBO)
- FIX Message Processing: Delivers FIX messages directly to CME iLink sessions
- 10G TCP Endpoint: Fully offloads Transmission Control Protocol (TCP) to FPGA logic
- Pre-built Triggers: Allows quote cancellation by product, group, or instrument
Customizable Cores in FPGA Logic:
- Pre-Trade Risk Checks: Supports implementation of client provided pre-trade risk checks
- Customizable Triggers: Available upon request
- C++ API: Pre-load trigger and orders
- GUI and RESTful Control Software: Parameters for configuration, status monitoring, and event logging
All of the above components are available in a turn-key server that includes Intel® Xeon CPU, FPGA Card, and 10GE NIC. Algo-Logic can drop ship the CME T2T System(s) to co-location in Aurora, IL.
About Algo-Logic Systems:
Algo-Logic Systems Inc., is a recognized leader that provides Gateware Defined Networking® products and solutions running on Field Programmable Gate Array (FPGA) devices complemented with open Application Programming Interfaces (APIs). Algo-Logic Systems products and solutions are used to lower latency in financial trading systems, increase packet throughput in datacenters and clouds, and lower energy consumption for data processing in embedded systems.
Price and availability: Call (408) 707-3747
For pricing and product info contact: firstname.lastname@example.org
For additional information please visit the company website at: www.algo-logic.com
*Gateware Defined Networking® is a registered trademark of Algo-Logic Systems, Inc.
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SOURCE Algo-Logic Systems