The new Cadence SiP Layout WLCSP option integrated with PVS provides generic silicon wafer-based packaging methodologies previously validated by TSMC for their Integrated Fan-Out (InFO) process. Enhancements to OrbitIO Interconnect Designer strengthen 2.5D interposer package design support, providing optimal multi-die, single package interconnect integration. This enables higher performance for multi-substrate integrated devices with minimal size optimized for signal performance. For more information on the Cadence IC packaging design and analysis solution, visit http://www.cadence.com/news/ICpackaging172.
"Wireless mobility and wireless-enabled is the trend at all levels of electronic-centric products, from smartphones to cars to home appliances and beyond. They all need thin, lightweight, low-power yet high-performance devices at their core. This is the sweet spot for WLCSP, fueling its predicted explosion in adoption," said Keith Felton, product management group director for the PCB Group at Cadence. "Our latest release enables broad WLCSP-enabled design and foundry and OSAT manufacturing signoff, which in turn helps fabless semiconductor and systems companies deliver ultra-thin mobile-focused devices using the latest foundry and OSAT IC package manufacturing approaches."
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com.
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SOURCE Cadence Design Systems, Inc.