Microsemi's Libero SoC v11.2 Software Reduces Compile Time by Up to 50 Percent for Company's Mainstream IGLOO2 FPGAs and SmartFusion2 SoC FPGAs Delivers Enhanced Ease-of-use, Power Analysis and Debug Features to FPGA and SoC Designers
ALISO VIEJO, Calif., Dec. 11, 2013 /PRNewswire/ -- Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced the release of the Libero System-on-Chip (SoC) version 11.2 comprehensive FPGA design software suite. This version greatly enhances productivity for designers using the mainstream features available in SmartFusion®2 SoC FPGAs and IGLOO®2 FPGAs. In this release, compile time can be reduced up to 50 percent for larger designs, and the addition of an incremental compilation option can further reduce compile time for all designs. Designers new to Microsemi FPGAs will benefit from enhancements to System Builder, the easy-to-use and correct-by-construction, step-by-step guide for configuring and implementing system designs. Additional productivity improvements include SmartDesign design canvas tool updates, SmartPower maximum process power analysis and thermal analysis capabilities, and SmartDebug SERDES physical media attachment (PMA) analysis features.
"Given the significant number of new customers adopting IGLOO2 and SmartFusion2 devices, we focused development on enhanced ease-of-use, faster run time, and expanded debug and analysis capabilities to improve customer productivity," said Shakeel Peera, director of Product Line Marketing for Microsemi's SoC product group. "In addition, designers of applications where power efficiency is a key concern can benefit from the new capabilities in the SmartPower analysis tool that demonstrates our mainstream FPGA families' industry-leading, ultra-low power consumption."
Key features in Libero SoC v11.2 include:
- Compile time reduction up to 50 percent for larger designs, and the addition of an incremental compilation option can further reduce compile time for all designs
- System Builder design tool for ARM®-based SoC design now offers an improved graphical interface with a broader range of integrated blocks and IP allowing fast and reliable automated system configuration and assembly
- Enhancements to SmartDesign, the easy-to-use, graphical, block-based design creation tool
- Introduction of Block Flow, a bottom up design methodology where design blocks are created, published, and instantiated in a top level design. These design blocks can have completed layout and optimized timing and power for a specific device, enabling more efficient design iterations while maintaining optimized performance and power.
- SmartDebug on-chip debug tool allows probing anywhere in the FPGA logic design without recompiling and now includes cutting-edge runtime SERDES debug features, enabling designers real-time optimization of their SERDES to achieve optimal signal integrity results
- SmartPower power analysis now supports maximum process analysis for the industry's lowest power mainstream FPGAs. IGLOO2 and SmartFusion2 devices demonstrate up to 10 times lower static power relative to other mainstream FPGAs and SoC FPGAs with similar capabilities.
- New device support and production timing. Design flow support for the M2S090 and M2GL090 devices (in all variants) and production timing support for the M2S050 and M2GL050 devices.
About Microsemi's SmartFusion2 SoC FPGAs
Microsemi's SmartFusion2 SoC FPGAs are the only devices that address fundamental requirements for advanced security, high reliability and low power in critical industrial, military, aviation, communications and medical applications. SmartFusion2 integrates an inherently reliable flash-based FPGA fabric, a 166 megahertz (MHz) ARM CortexTM-M3 processor, advanced security processing accelerators, DSP blocks, SRAM, eNVM and industry-required high-performance communication interfaces all on a single chip.
About Microsemi's IGLOO2 FPGAs
Microsemi's IGLOO2 FPGAs continue the company's focus on addressing the needs of today's cost-optimized FPGA market by providing a LUT-based fabric, 5G transceiver, high speed GPIO, block RAM, high-performance memory subsystem, and DSP blocks in a differentiated, cost and power optimized architecture. This next generation IGLOO2 architecture offers up to five times more logic density and three times more fabric performance than its predecessors and combines a non-volatile Flash-based fabric with the highest number of general purpose I/O, 5G SERDES interfaces and PCIe end points when compared to other products in its class. IGLOO2 FPGAs offer best-in-class feature integration coupled with the lowest power, highest reliability and most advanced security in the industry.
Libero SoC v11.2 software toolset is now available for download from Microsemi's website at http://www.microsemi.com/products/fpga-soc/design-resources/design-software/libero-soc#downloads.
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 3,000 employees globally. Learn more at www.microsemi.com.
Microsemi and the Microsemi logo are registered trademarks or service marks of Microsemi Corporation and/or its affiliates. Third-party trademarks and service marks mentioned herein are the property of their respective owners.
"Safe Harbor" Statement under the Private Securities Litigation Reform Act of 1995: Any statements set forth in this news release that are not entirely historical and factual in nature, including without limitation statements related to its Libero System-on-Chip version 11.2 comprehensive FPGA design software suite, and its potential effects on future business, are forward-looking statements. These forward-looking statements are based on our current expectations and are inherently subject to risks and uncertainties that could cause actual results to differ materially from those expressed in the forward-looking statements. The potential risks and uncertainties include, but are not limited to, such factors as rapidly changing technology and product obsolescence, potential cost increases, variations in customer order preferences, weakness or competitive pricing environment of the marketplace, uncertain demand for and acceptance of the company's products, adverse circumstances in any of our end markets, results of in-process or planned development or marketing and promotional campaigns, difficulties foreseeing future demand, potential non-realization of expected orders or non-realization of backlog, product returns, product liability, and other potential unexpected business and economic conditions or adverse changes in current or expected industry conditions, difficulties and costs of protecting patents and other proprietary rights, inventory obsolescence and difficulties regarding customer qualification of products. In addition to these factors and any other factors mentioned elsewhere in this news release, the reader should refer as well to the factors, uncertainties or risks identified in the company's most recent Form 10-K and all subsequent Form 10-Q reports filed by Microsemi with the SEC. Additional risk factors may be identified from time to time in Microsemi's future filings. The forward-looking statements included in this release speak only as of the date hereof, and Microsemi does not undertake any obligation to update these forward-looking statements to reflect subsequent events or circumstances.
SOURCE Microsemi Corporation