ALISO VIEJO, Calif., March 10, 2016 /PRNewswire/ -- Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced the release of the latest version of Libero system-on-chip (SoC), version 11.7, a comprehensive suite of FPGA design tools used with the company's field programmable gate array (FPGA) products. The latest software release includes a number of new features to enhance ease-of-use and efficiency for designers, as well as advanced security and evaluation tools, for its RTG4™ FPGAs, SmartFusion™2 SoC FPGAs and IGLOO™2 FPGAs.
"The release of our Libero SoC v11.7 software offers a significantly improved user experience due to a new and enhanced constraints flow with a new constraints management view, a fully redesigned ChipPlanner and a new simultaneous switching noise (SSN) analyzer," said Jim Davis, vice president of software engineering at Microsemi. "Customers will also benefit greatly from SmartDebug updates with improved navigation of the user's design, an improved remote workflow installation and a Serializer/Deserializer (SerDes) BER calculator. Additionally, productivity has been greatly accelerated with a SmartTime UI that is two times faster and the SmartPower tool working five times faster in processing designs."
In addition to the usability features, which support faster time-to-market for designers of FPGA-based solutions, Microsemi's Libero SoC v11.7 release also marks the production release of its Secured Production Programming Solution (SPPS) which is used to prevent overbuilding, cloning, reverse engineering, malware insertion and other security threats.
Improved User Experience
Libero v11.7 introduces an enhanced constraints flow aimed at simplifying the management of all constraints in a design. The solution is used to manage timing constraints, input/output (I/O) attribute constraints, floor planning constraints and netlist attribute constraints to ensure they can be created, imported, edited and organized in a single view. Timing constraints only need to be entered once, and can be automatically applied in synthesis, timing-driven place and route, and timing verification. Timing constraints for known hardware blocks and intellectual property (IP) elements are derived automatically.
The new software release also features a fully redesigned ChipPlanner, a floor planning tool used to define and assign logic to regions within the FPGA. This design technique is particularly useful for controlling design placement in order to obtain optimal results. The new ChipPlanner also includes interface updates and significant runtime enhancements, most notably on large and highly utilized designs.
For the SmartFusion2, IGLOO2, and RTG4 families, SmartDebug allows unprecedented visibility into FPGA designs without the need to reinstrument and rebuild the design. With SmartDebug, users can read and write to any FPGA fabric flip-flops using active probes, or view any two flip-flops on the PRA/PRB pins via an external scope using live probes. In addition SmartDebug allows users to read and write to LSRAM, uSRAM and SerDes control registers. In Libero SoC v11.7, Microsemi is further enhancing SmartDebug with uniform fabric probe selection and design navigation for active or live probes, and a standalone version which allows for a lightweight lab installation.
According to the Aberdeen group, by the year 2020 approximately 50 billion machines will be connected. Not only do these machines need to be secure, they need to be secured at the device, design and system levels.
Libero v11.7 introduces the company's SPPS, which enables secured production programming of Microsemi's SmartFusion2 SoC FPGAs and IGLOO2 FPGAs. SPPS securely generates and injects cryptographic keys and configuration bitstreams into Microsemi's FPGAs which could prevent cloning, reverse engineering, malware insertion, leakage of sensitive intellectual property (IP) such as trade secrets or classified data, overbuilding and potentially protect against other security threats.
Microsemi's SPPS uses Federal Information Processing Standards (FIPS)-certified hardware security modules (HSMs) for critical computations, in conjunction with Microsemi's tamper-resistant flash FPGAs. This prevents today's major security threats by external adversaries or competitors, unscrupulous contract manufacturers and their employees, or other insiders.
Other New Features
Libero SoC v11.7 also includes several other updates, some of these are mentioned below. For more information, please refer to the detailed release notes.
- New SSN analyzer tool support to compute noise margin for each FPGA pin
- Five times runtime improvement on SmartPower
- Two times user interface (UI) runtime improvement on SmartTime
- Multi-corner analysis support for SmartTime
- Cross clock domain optimization in physical design
The Libero SoC v11.7 software toolset is now available for download from Microsemi's website at www.microsemi.com/products/fpga-soc/design-resources/design-software/libero-soc#downloads. For more information, contact firstname.lastname@example.org.
About Microsemi's IGLOO2 FPGAs and SmartFusion2 SoC FPGAs
Microsemi's IGLOO2 FPGAs and SmartFusion2 SoC FPGAs deliver more resources in low density devices, with the lowest power, proven security and exceptional reliability. The devices offer 30-50 percent more power efficiency and are ideal for general purpose functions such as Gigabit Ethernet or dual PCI Express control planes, bridging functions, input/output (I/O) expansion and conversion, video/image processing, system management and secure connectivity. Microsemi FPGAs and SoC FPGAs are used by customers in communications, industrial, medical, defense and aviation markets. PCIe Gen 2 connectivity starts at just 10K logic elements (LEs). SmartFusion2 SoC FPGAs offer a 166MHz ARM Cortex-M3 processor with up to 512KB of embedded flash and a complete peripheral set. IGLOO2 FPGAs offer a high performance memory subsystem with up to 512KB embedded flash, 2 x 32 KB embedded static random-access memory (SRAM), two direct memory access (DMA) engines and two double date rate (DDR) controllers. Microsemi also offers a broad range of military, automotive and space grade FPGAs and SoC FPGAs. For more information visit: http://www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion2 and http://www.microsemi.com/products/fpga-soc/fpga/igloo2-fpga
About Microsemi's RTG4 FPGAs
RTG4 FPGAs bring new capabilities to the market and combine a wealth of features with the highest quality and reliability to meet the increasing demands of modern satellite payloads. The devices feature reprogrammable flash configuration, making prototyping easier for customers. RTG4's reprogrammable flash technology offers complete immunity to radiation-induced configuration upsets in the harshest radiation environments, without the configuration scrubbing required with SRAM FPGA technology. RTG4 supports space applications requiring up to 150,000 logic elements and up to 300 MHz of system performance. RTG4 is Microsemi's latest development in a long history of radiation-tolerant FPGAs that are found in many NASA and international space programs. For more information, visit http://www.microsemi.com/products/fpga-soc/radtolerant-fpgas/rtg4.
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 4,800 employees globally. Learn more at www.microsemi.com.
Microsemi and the Microsemi logo are registered trademarks or service marks of Microsemi Corporation and/or its affiliates. Third-party trademarks and service marks mentioned herein are the property of their respective owners.
"Safe Harbor" Statement under the Private Securities Litigation Reform Act of 1995: Any statements set forth in this news release that are not entirely historical and factual in nature, including without limitation, statements related to its updated Libero system-on-chip (SoC) version 11.7 comprehensive design software tool used for the development of the company's field programmable gate array (FPGA) products, are forward-looking statements. These forward-looking statements are based on our current expectations and are inherently subject to risks and uncertainties that could cause actual results to differ materially from those expressed in the forward-looking statements. The potential risks and uncertainties include, but are not limited to, such factors as rapidly changing technology and product obsolescence, potential cost increases, variations in customer order preferences, weakness or competitive pricing environment of the marketplace, uncertain demand for and acceptance of the company's products, adverse circumstances in any of our end markets, results of in-process or planned development or marketing and promotional campaigns, difficulties foreseeing future demand, potential non-realization of expected orders or non-realization of backlog, product returns, product liability, and other potential unexpected business and economic conditions or adverse changes in current or expected industry conditions, difficulties and costs of protecting patents and other proprietary rights, inventory obsolescence and difficulties regarding customer qualification of products. In addition to these factors and any other factors mentioned elsewhere in this news release, the reader should refer as well to the factors, uncertainties or risks identified in the company's most recent Form 10-K and all subsequent Form 10-Q reports filed by Microsemi with the SEC. Additional risk factors may be identified from time to time in Microsemi's future filings. The forward-looking statements included in this release speak only as of the date hereof, and Microsemi does not undertake any obligation to update these forward-looking statements to reflect subsequent events or circumstances.
SOURCE Microsemi Corporation