Synopsys, Inc. (Nasdaq: SNPS) today announced its collaboration with TSMC to develop DesignWare® Interface, Analog and Foundation IP for TSMC's 12FFC process. By offering a wide range of IP on TSMC's latest low-power process, Synopsys is enabling designers to take advantage of the low leakage and small area advantages of the new process. Synopsys and TSMC have partnered on the development of Synopsys IP for advanced process technologies for more than two decades, resulting in a robust portfolio of IP supporting process technologies down to 7nm. Synopsys DesignWare IP for the 12FFC process enables designers to accelerate development of mobile SoCs that incorporate logic libraries, embedded memories, embedded test and repair, USB 3.1/3.0/2.0, USB-C 3.1/DisplayPort 1.3, DDR4/3, LPDDR4X, PCI Express® 4.0/3.1/2.1, SATA 6G, HDMI 2.0, MIPI M-PHY and D-PHY and data converter IP.
"TSMC and Synopsys share a long history of providing designers with a wide range of high-quality IP on TSMC's advanced FinFET processes," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "By developing IP on the latest TSMC 12FFC process, Synopsys is paving the way for designers to improve their SoCs' leakage and lower overall costs."
"As SoCs continue to incorporate more advanced functionality, designers are constantly challenged with meeting aggressive performance, power and area requirements," said John Koeter, vice president of marketing for IP at Synopsys. "Our close collaboration with TSMC on the development of a broad range of IP for the 12FFC process will ensure that designers have timely access to the high-quality, proven IP solutions they need to achieve their design goals and quickly get their product to market."
The DesignWare IP for USB 2.0/3.0/3.1/Type-C, DisplayPort, PCI Express 4.0/3.0/2.0, SATA 6G, MIPI D-PHY/M-PHY, 25G Ethernet, HDMI 2.0, DDR4/3 and LPDDR4X, and 12-bit data converters are expected to be available for TSMC's 12FFC process in Q3 2017.
About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit http://www.synopsys.com/designware.
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
This press release contains forward-looking statements within the meaning of Section 21E of the Securities Exchange Act of 1934, including statements regarding the expected release and benefits of DesignWare IP for USB 2.0/3.0/3.1/Type-C, DisplayPort, PCI Express 4.0/3.0/2.0, SATA 6G, MIPI D-PHY/M-PHY, 25G Ethernet, HDMI 2.0, DDR4/3 and LPDDR4X, and 12-bit data converters. Any statements that are not statements of historical fact may be deemed to be forward-looking statements. These statements involve known and unknown risks, uncertainties and other factors that could cause actual results, time frames or achievements to differ materially from those expressed or implied in the forward-looking statements. Other risks and uncertainties that may apply are set forth in the "Risk Factors" section of Synopsys' most recently filed Annual Report on Form 10-K. Synopsys undertakes no obligation to update publicly any forward-looking statements, or to update the reasons actual results could differ materially from those anticipated in these forward-looking statements, even if new information becomes available in the future.
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SOURCE Synopsys, Inc.