MOUNTAIN VIEW, Calif., May 24, 2017 /PRNewswire/ --
- 8LPP and 7LPP implementation flows fully enabled in IC Compiler II place and route, Design Compiler Graphical synthesis, IC Validator physical signoff and StarRC extraction tools
- 8LPP test chip taped out with Synopsys Design Platform
- Synopsys Process Design Kits now available for both processes
Synopsys, Inc. (Nasdaq: SNPS) today announced that Samsung Electronics Co., Ltd. has enabled the Synopsys Design Platform for Samsung's 8LPP (Low-Power Plus) and 7LPP process technologies. Samsung's 8LPP, a process derivative of 10LPP, offers smaller area when compared to 10LPP with minimal impact to the 10-nm design methodology. Synopsys Design Platform, silicon-proven at 10LPP, is being confidently deployed by early adopters of the 8LPP and 7LPP processes. This enablement includes delivery of comprehensive Process Design Kits (PDKs) that include routing rules, physical verification runsets for DRC and LVS, signoff-accurate extraction technology files and SPICE models for 8LPP and 7LPP process technologies.
Anchored by IC Compiler II and Design Compiler Graphical, the complete physical implementation solution has been enabled with new design rules for 8LPP and 7LPP process technologies. The platform supports sophisticated multi-patterning requirements for the 8LPP process. It has been enhanced for 7LPP to handle extreme ultraviolet (EUV) single pattern-based routing and power network via stapling for improved reliability.
"Built on a long history of deep collaboration with Synopsys, platform enablement allows our mutual customers to design the most competitive 8LPP and 7LPP system on chip (SoC) products," said Jaehong Park, senior vice president of the Foundry Design Team at Samsung Electronics. "Our foundry customers can rapidly and confidently ramp their designs to volume production on all of our advanced FinFET-based processes using the Synopsys Design Platform."
"Our collaboration with Samsung Foundry is focused on enabling designers to get the optimum QoR on Samsung Foundry's most advanced FinFET process technologies," said Michael Jackson, corporate vice president of marketing and business development for Synopsys' Design Group. "With tapeouts already completed, our mutual customers can confidently deploy Synopsys Design Platform for their 8LPP or 7LPP SoC designs."
Synopsys Design Platform PDKs are available from Samsung for early access engagements. Key tools and features of the Synopsys Design Platform enabled for 8LPP and 7LPP process technologies include:
- IC Compiler II™ place and route solution: Single through multi-pattern and color-aware physical implementation
- Design Compiler® Graphical RTL synthesis: Correlation, congestion reduction, and physical guidance for IC Compiler II
- IC Validator signoff physical verification: In-Design, automated single through multi-patterning DRC repair, DFM pattern matching and DFM metal fill within IC Compiler II place-and-route system; and LVS signoff
- StarRC™ extraction: Single through multi-patterning, full color-aware variation and 3D FinFET modeling
- HSPICE® simulation: Device modeling with self-heating effect and accurate simulation of analog, high-frequency and SRAM designs
To learn more, attend the Samsung Foundry Forum on May 24, 2017 at the Santa Clara Marriott.
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
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SOURCE Synopsys, Inc.