Tachyon Design Automation Announces Major CVC Verilog Compiler Release
New features provide unique FST wave form dumping and toggle coverage
MINNEAPOLIS, July 10, 2013 /PRNewswire/ -- Tachyon Design Automation today announced a major release 6.5 of CVC compiled Verilog simulator. CVC 6.5 adds precisely controllable net toggle recording and reporting along with simplified test bench toggle result merging. Capacity and speed of value change dumping to FST format value change files (supported by the GTKWave wave form viewer) has been improved so that wave form dumping has almost no overhead because unused CPU cores process and output FST value changes.
"With CVC's high speed and recent improvements in computer performance, utilizing accurate delay Verilog simulation results to improve design understanding and power saving has become a problem. CVC 6.5 is the only commercial quality Verilog simulator that supports the new fastest and smallest file size FST wave form dump format. CVC utilizes unused processor cores to eliminate most dumping overhead. The new toggle coverage feature provides accurate and precise information about signal switching that no static analysis tool can possibly calculate again with almost no reduction in simulation speed." stated Steven Meyer, President of Tachyon DA.
About CVC and Tachyon Design Automation
Tachyon Design Automation specializes in electronic design automation (EDA) software. Our flagship CVC product is a fast full IEEE 1364 standard high capacity compiled digital Verilog simulator.
For more information visit Tachyon DA web site www.tachyon-da.com. To determine CVC pricing or to evaluate CVC contact Tachyon Design Automation sales at 612-371-2023 or send email to email@example.com. To see CVC's superior speed, download and run open core benchmarks from www.tachyon-da.com/verilog_benchmarks.htm and compare results against your current Verilog simulator.
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SOURCE Tachyon Design Automation Corp.
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